NEC V850E/PH2, User Manual

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Chapter 17 Clocked Serial Interface 3 (CSI3)
User’s Manual U16580EE3V1UD00
Figure 17-21: Transfer Wait Function (2/3)
(b) Transfer Wait Enabled (CSWEn Bit = 1),
INTC3n Delay Disabled (CSITn Bit = 0),
CKPn and DAPn Bits = 00B,
Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B),
Intermediate Inactive Chip Select Level Enabled (CSMDn = 1)
Remarks: 1. When the CSIBUFn register is empty at the time of <1>, the chip select pins output an
inactive level and maintain it.
When the CSIBUFn register is not empty at the time of <1>, the chip select pins output
an inactive level up to the time of <2>, and output subsequently the succeeding chip
select data
Moreover, in single mode (TRMDn bit of the CSIM3n register = 0) the chip select pins
output an inactive level from the time <1> and held it pending until the previously receive
data is read from the SIRB3n register and the SIRB3n register becomes empty.
2.
μ
PD70F3187: n = 0, 1
μ
PD70F3447: n = 0
DI7 DI6 DI5
DO7
CS data
<1> <2>
CS data
DO6 DO5
SCK3n (output)
SI3n (input)
SO3n (output)
INTC3n interrupt
SCS3n0 to
SCS3n3 (outputs)
DI7 DI1 DI0
Wait
DO1 DO0 DO7