NEC V850E/PH2, User Manual

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Chapter 9 16-Bit Timer/Event Counter P
User’s Manual U16580EE3V1UD00
9.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110B)
In the pulse width measurement mode, free-running count is performed. The value of the 16-bit counter
is saved to capture register 0 (TPnCCR0), or capture register 1 (TPnCCR1) respectively, and the 16-bit
counter is cleared upon edge detection of the TIPn0 pin, or TIPn1 respectively. The external input pulse
width can be measured as a result.
However, when measuring a large pulse width that exceeds 16-bit counter overflow, perform judgment
with the overflow flag. Since measurement of pulses for which overflow occurs twice or more is not
possible, adjust the operating frequency of the 16-bit counter.
Depending on the selected capture input sources and specified edge detection three different
measurement methods can be applied.
<1> Pulse period measurement
<2> Alternating pulse width and pulse space measurement:
This requires a fast interrupt handling, in order to measure pulse width and pulse space correctly.
<3> Simultaneous pulse width and pulse space measurement:
Both capture inputs are required to measure pulse width and pulse space simultaneously.
The measurements methods are explained in the following sub-chapters.
Cautions: 1. In the pulse width measurement mode, the external event clock input (TEVTPn) is
prohibited (TPnCTL1.TPnEEE = 0).
2. When an internal count clock
≤
f
XX
/16 (TPnCTL0.TPnCKS2-0) is selected in pulse
width measurement mode, and a valid signal edge is input before the first count
up, the a value of FFFFH will be captured in the corresponding TPnCCR0 or
TPnCCR1 register.
3. Pulse width measurement cannot be performed by timer P8 (TMP8).
Remark: n = 0 to 7