NEC V850E/PH2, User Manual

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Chapter 18 AFCAN Controller
User’s Manual U16580EE3V1UD00
(2) Status in CAN stop mode
The CAN module is in the following state after it enters the CAN stop mode.
• The internal operating clock is stopped and the power consumption is minimized.
• To wake up the CAN module from the CPU, data can be written to the PSMODE[1:0] bits of the CAN
module control register (CnCTRL), but nothing can be written to other CAN module registers or bits.
• The CAN module registers can be read, except for the CnLIPT, CnRGPT, CnLOPT, and CnTGPT
registers.
• The CAN message buffer registers cannot be written or read.
• MBON bit of the CAN Global Control register (CnGMCTRL) is cleared.
• An initialization mode transition request is not acknowledged and is ignored.
(3) Releasing CAN stop mode
The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bits of the CnCTRL
register. After releasing the CAN stop mode, the CAN module enters the CAN sleep mode.
When the initialization mode is requested while the CAN module is in the CAN stop mode, that
request is ignored; the CPU has to release the stop mode and subsequently CAN sleep mode
before entering the initialization mode. It is impossible to enter the other operation mode directly
from the CAN stop mode not entering the CAN sleep mode, that request is ignored.
18.11.3 Example of using power saving modes
In some application systems, it may be necessary to place the CPU in a power saving mode to reduce
the power consumption. By using the power saving mode specific to the CAN module and the power
saving mode specific to the CPU in combination, the CPU can be woken up from the power saving sta-
tus by the CAN bus.
Here is an example for using the power saving modes.
• First, put the CAN module in the CAN sleep mode (PSMODE[1:0] = 01B). Next, put the CPU in the
power saving mode. If an edge transition from recessive to dominant is detected at the CAN recep-
tion pin (CRXDn) in this status, the CINTS5 bit in the CAN module is set to 1. If the CIE5 bit of the
CnCTRL register is set to 1, a wakeup interrupt (INTWUPn) is generated.
• The CAN module is automatically released from CAN sleep mode (PSMODE = 00B) and returns to
normal operation mode.
• The CPU, in response to INTWUPn, can release its own power saving mode and return to normal
operation mode.
To further reduce the power consumption of the CPU, the internal clocks— including that of the CAN
module—may be stopped. In this case, the operating clock supplied to the CAN module is stopped
after the CAN module has been put in CAN sleep mode. Then the CPU enters a power saving mode
in which the clock supplied to the CPU is stopped.
• If an edge transition from recessive to dominant is detected at the CAN reception pin (CRXDn) in
this status, the CAN module can set the CINTS5 bit to 1 and generate the wakeup interrupt
(INTWUPn) even if it is not supplied with the clock.
• The other functions, however, do not operate, because clock supply to the CAN module is stopped,
and the module remains in CAN sleep mode.
• The CPU, in response to INTWUPn