NEC V850E/PH2, User Manual

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Chapter 10 16-bit Inverter Timer/Counter R
User’s Manual U16580EE3V1UD00
10.5.1 Compare match interrupt related cautions
(1) Cautions in high-accuracy T-PWM mode
Compare match interrupts occur upon a match between the counter and a compare register
(TRnCCR0 to TRnCCR5). However, in the high-accuracy T-PWM mode, the compare register can
be set exceeding the counter’s count operation range. Therefore, under the following conditions,
no compare interrupt is output.
• Restrictions related to compare match interrupt with TRnCCR0 register (INTTRnCC0)
In the high-accuracy T-PWM mode, when TRnDTC1
≠
000H, no compare match interrupt
(INTTRnCC0) is output.
(Use INTTRnOD (valley interrupt) and INTTRnCD (peak interrupt) as the cycle interrupts.)
• Restrictions related to TRnCCR1 to TRnCCR3 register
In the high-accuracy T-PWM mode, if set in the range of 0000H
≤
TRnCCRm < TRnDTC0,
(TRnCCR0 - TRnDTC1) < TRnCCRm
≤
TRnCCR0, no interrupt occurs upon a match between
the compare value and the counter.
Remark: m = 1 to 3
• Restrictions related to TRnCCR4 and TRnCCR5 registers
In the high-accuracy T-PWM mode, if set in the range of 0000H
≤
TRnCCR4, TRnCCR5 <
TRnDTC0, (TRnCCR0 - TRnDTC1) < TRnCCR4, TRnCCR5
≤
TRnCCR0, no compare match
interrupt is output since no match between the compare value and counter occurs.
When TRnCCR4 and TRnCCR5 registers are used as trigger causes for A/D triggers, perform
setting in the range of TRnDTC0
≤
TRnCCR4, TRnCCR5
≤
(TRnCCR0 - TRnDTC1).
TRnCNT
TRnSBC
0000H
TRnDTC0
TRnCCR0
-TRnDTC1
TRnCCR0
TRnCCRm setting range in which
no INTTRnCC1m interrupt occurs
TRnCCRm setting range in which
INTTRnCC1m interrupt occurs
TRnCCRm setting range in which
no INTTRnCC1m interrupt occurs
TRnCNT
TRnSBC
0000H
TRnDTC0
TRnCCR0
-TRnDTC1
TRnCCR0
Setting range of TRnCCR4 or TRnCCR5,
in which INTTRnCC4 or INTTRnCC5
interrupts occur