NEC V850E/PH2, User Manual

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Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10)
User’s Manual U16580EE3V1UD00
(2) Timer control register 10 (TMC10)
The TMC10 register is used to enable/disable TMENC10 operation and to set transfer and timer
clear operations.
This register can be read/written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution: Changing the values of the TMC10 register bits other than the TM1CE bit during
TMENC10 operation (TM1CE bit = 1) is prohibited.
Figure 12-8: Timer Control Register 10 (TMC10) (1/2)
After reset: 00H R/W Address: FFFFF6BCH
7 6 5 4 3 2 1 0
TMC10 0 TM1CE 0 0 RLEN ENMD CLR1 CLR0
TM1CE TMENC10 Operation Control
0 Count operation disabled
1 Count operation enabled
RLEN Transfer Operation Control in UDC Mode A
0 Transfer operation from CM100 register to TMENC10 disabled
1 Transfer operation from CM100 register to TMENC10 enabled
• When RLEN = 1, the value set to CM100 is transferred to TMENC10 upon occurrence
of TMENC10 underflow.
• When the CMD bit of the TUM10 register = 0 (general-purpose timer mode), the RLEN
bit settings are invalid, and a transfer operation is not executed even if the RLEN bit is
set to 1.
• When the MSEL bit of the TUM10 register = 1 (UDC mode B), the RLEN bit settings
are invalid, and a transfer operation is not executed even if the RLEN bit is set to 1.
ENMD Clear Operation Control in General Purpose Mode
0 Clear disabled (free-running mode)
Clearing is not performed even when TMENC10 and CM100 values match.
1 Clear enabled
Clearing is performed upon match of TMENC10 and CM100 values.
When the CMD bit of the TUM10 register = 1 (UDC mode), the ENMD bit setting becomes
invalid.