NEC V850E/PH2, User Manual

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Chapter 16 Clocked Serial Interface B (CSIB)
User’s Manual U16580EE3V1UD00
Figure 16-4: CSIBn Control Register 0 (CBnCTL0) (2/2)
Note: Rewrite is possible only when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be set
at the same time.
Remark:
μ
PD70F3187: n = 0, 1
μ
PD70F3447: n = 0
CBnDIR
Note
Transfer Direction Selection
0 MSB-first transfer
1 LSB-first transfer
CBnSSE
Note Slave Selection Operation Enable
0 Slave selection function disabled
1 Slave selection function enabled
When the CSIBn serves as slave, it executes transmission/reception in synchronization
with the clock only when a low level is input to the SSBn pin.
CBnTMS
Note Transfer Mode Selection
0 Single transfer mode
1 Continuous transfer mode
When the CBnTMS bit = 0, the single transfer mode is entered, so continuous
transmission/continuous reception are not supported. Even in the case of transmission
only, an interrupt is output upon completion of reception transfer.
CBnSCE Serial Clock Enable
0 Clock output stopped
1 Clock output enabled
The transfer clock is stopped after the last data in the master reception mode.
Clear (0) the CBnSCE bit prior to when the last data is read in the single transfer mode,
and 1 clock before the completion of reception of the last data in the continuous transfer
mode.
The transfer clock can be output by setting the CBnSCE bit to 1 again after the last data
has been read.