NEC V850E/PH2, User Manual

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Chapter 17 Clocked Serial Interface 3 (CSI3)
User’s Manual U16580EE3V1UD00
(3) SCS3n0 to SCS3n3 pins
The SCS3n0 to SCS3n3 pins output the default level when both the CTXEn and CRXEn bits of the
CSIM3n register are 0, or when the CSICAEn bit of the CSIM3n register is cleared to 0 (n = 0, 1).
These pins output the default level when the FPCLRn bit of the SFA3n register is set to 1. In slave
mode these pins output always the default level (inactive level).
Table 17-5: Default Output Level of SCS3n0 to SCS3n3 Pins
Note: Default value after reset.
Remark:
μ
PD70F3187: n = 0, 1
μ
PD70F3447: n = 0
17.5.17 CSIBUFn overflow interrupt signal (INTC3nOVF)
The INTC3nOVF interrupt is output when 16 data exist in the CSIBUFn register and when the 17th data
is written (to the SFDB3n or SFDB3nL register). The 17th data is not written but ignored.
In the single mode (TRMDn bit of the CSIM3n register = 0), 16 data exist in the CSIBUFn register when
“write CSIBUFn pointer value = SIO3n load CSIBUFn pointer value” and SFFULn bit of the SFA3n
register = 1. When transfer is completed and the SIO3n load CSIBUFn pointer is incremented, the
CSIBUFn register has one vacancy (the CSIBUFn register has no vacancy even when transfer of one
data has been completed in the consecutive mode (TRMDn bit = 1)).
CSLVn Bit Default Output Level of SCS3n0 to SCS3n3 Pins
0
High level
Note
1 Low level