NEC V850E/PH2, User Manual

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Chapter 10 16-bit Inverter Timer/Counter R
User’s Manual U16580EE3V1UD00
Figure 10-19: TMRn Option Register 0 (TRnOPT0) (2/2)
Remark: n = 0, 1
TRnCMS Compare Register Transfer Timing Mode Selection
0 Reload mode (batch rewrite):
When the TRnCCR1 register is written to, all the registers are updated at the
next reload timing (reload). Even if registers other than the TRnCCR1 register
are written, reload is not executed.
1 Anytime rewrite mode:
Each register is updated independently, and when write access is performed to
a compare register, the register is updated to the value used during anytime
write access.
Several clocks are required until the value is transferred to the register
following write. (Refer to
10.4.2 (1) Anytime rewrite .)
Remark: The TRnCMS bit is valid only in the high-accuracy T-PWM mode, In all other
modes it is invalid and has to be cleared (TRnCMS = 0).
TRnCUF Timer R Counter Up/Down Detection Flag
0 The timer counter is in up count state.
1 The timer counter is in down count state.
Remark: The TRnCUF bit is valid only in the high-accuracy T-PWM mode and triangular
wave PWM mode. In all other modes, it is invalid (TRnCUF = 0).
TRnOVF Timer R Overflow Detection Flag
0 No overflow occurrence (after bit was cleared)
1 Overflow occurrence
Remarks: 1. The TRnOVF bit is set (1) when the 16-bit counter value overflows from
FFFFH to 0000H.
2. The TRnOVF bit is cleared (0) when either 0 is written to it, or TRnCE = 0 is
set.
3. When TRnOVF bit is set (1), an overflow interrupt (INTTRnOV) is
simultaneously output.
Cautions: 1. Overflow can only occur in the free-running mode and the T-PWM
mode. If, in the high-accuracy T-PWM mode, the set conditions for the
TRnDTC0 and TRnDTC1 registers are incorrect, the TRnOVF bit may
be set (1).
2. When TRnOVF = 1, even if the TRnOVF bit and the TRnOPT0 register
are read, the TRnOVF bit is not cleared.
3. The TRnOVF bit can be read and written, but even if “1” is written to
TRnOVF bit from the CPU, this is ignored.