NEC V850E/PH2, User Manual

Page: 719 / 1053

719
Chapter 17 Clocked Serial Interface 3 (CSI3)
User’s Manual U16580EE3V1UD00
<1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled.
<2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers.
<3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0.
<4> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n
register.
<5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the
CSIM3n register and, at the same time, enable transmission/reception by setting the CTXEn and
CRXEn bits to 1.
<6> Confirm that the SFFULn bit of the SFA3n register is 0, and then write first CS data to the
SFCS3n register and subsequently write transfer data to the SFDB3n register.
If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the
interrupt servicing routine of INTC3n, it is not always necessary to confirm that the SFFULn bit is
0.
<7> Confirm that the INTC3n interrupt has occurred, and then read the SIRB3n register.
<8> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1, and disable
transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end
of transmission/reception).
Remarks: 1. To execute a further transfer, repeat <6> before <7>.
2.
μ
PD70F3187: n = 0, 1
μ
PD70F3447: n = 0