NEC V850E/PH2, User Manual

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Chapter 3 CPU Functions
User’s Manual U16580EE3V1UD00
3.4.7 Programmable peripheral I/O area
In the V850E/PH2, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O
area. In this area, the area between x0000H and x08FFH is used exclusively for the CAN controllers
(CAN0, CAN1
Note
).
The internal bus of the V850E/PH2 becomes active when the on-chip peripheral I/O register area
(FFFF000H to FFFFFFFH) or the programmable peripheral I/O register area (xxxxm000H to
xxxxnFFFH) is accessed (m = xx00B, n= xx11B). However, the on-chip peripheral I/O area is allocated
to the last 4 KB of the programmable peripheral I/O register area. Note that when data is written to this
area, the written contents are reflected on the on-chip peripheral I/O area. Therefore, access to this
area is prohibited. To access the on-chip peripheral I/O area, be sure to specify addresses FFFF000H
to FFFFFFFH.
Figure 3-23: Programmable Peripheral I/O Area (Outline)
Remark: M = xx00B, N = M + 11B, P= M + 10B
Cautions: 1. It is recommended to locate the programmable peripheral area in the first
32 Mbyte of the physical memory.
2. The programmable peripheral area is not allowed to overlap the ROM or RAM
areas: BPC must be initialized with a value in the range 0040H to 0FFBH.
Note: CAN1 not available for
μ
PD70F3447.
3FFFFFFH
3FFF000H
3FFEFFFH
xxxxNFFFH
xxxxM000H
x3FFFH
x3000H
x2FFFH
x0000H
x08FFH
0000000H
Peripheral
I/O register
Programmable
peripheral
I/O register
Internal local bus
Dedicated area for
CAN controllers
On-chip peripheral
I/O area
Programmable
peripheral
I/O area