NEC V850E/PH2, User Manual

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Chapter 10 16-bit Inverter Timer/Counter R
User’s Manual U16580EE3V1UD00
Rewrite in <3> interval (rewrite before match occurrence)
In the case of rewrite before a match between the TRnCCR1 to TRnCCR3 registers and the
counter occurs, a match with the counter occurs following rewrite and the rewrite value is instantly
reflected.
If a value larger than the counter value is written before match occurrence, no match occurs, so
the following output wave results.
If no match occurs, the timer output remains unchanged.
However, even if a match occurs, the timer output is forcibly changed to normal phase inactive
level at valleys.
Counter
TRnCCR1
“i”
“k”
TRnCCR1
buffer
TORn1
“k” “k”
TORn2
“i”
“i”
“k”
“k”
Counter
TRnCCR1
“i”
TRnCCR1
buffer
TORn1
“r” “r” “r”
Forced fall
TORn2
“i”
“i”
“r”
“r”