NEC V850E/PH2, User Manual

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Chapter 16 Clocked Serial Interface B (CSIB)
User’s Manual U16580EE3V1UD00
16.4.2 Single transfer mode (master mode, transmission mode)
Figure 16-10: Single Transfer Mode (Master Mode, Transmission Mode)
MSB First (CBnDIR Bit of CBnCTL0 Register = 0),
CBnCKP Bit of the CBnCTL1 Register = 0,
CBnDAP Bit of the CBnCTL1 Register = 0,
Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B)
<1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
<2> Set the CBnTXE bit of the CBnCTL0 register to 1 at the same time as specifying the transfer
mode using the CBnDIR bit of the CBnCTL0 register, to set the transmission/reception enable
status.
<3> Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply.
<4> Write transfer data to the CBnTX register (transmission start).
<5> The reception complete interrupt (INTCBnR) is output, notifying the CPU that writing the CBnTX
(CBnTXL) register is possible.
<6> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop
clock supply to CSIB (end of transmission/reception).
To continue transfer, repeat steps <4> and <5> before <6>.
Remarks: 1. The processing of steps <2> and <3> can be set simultaneously.
2.
μ
PD70F3187: n = 0, 1
μ
PD70F3447: n = 0
CBnTX register write (55H)
AAH 54H A8H 50H A0H 40H 80H 00H
55H (transmit data)
CBnTX
register
Shift
register n
<1> <4> <5> <6>
<2>
<3>
SCKBn pin
INTCBnR
signal
SIBn pin
CBnTSF bit
(55H)
0 1 0 0 1 0
L
1
1 SOBn pin