NEC V850E/PH2, User Manual

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Chapter 10 16-bit Inverter Timer/Counter R
User’s Manual U16580EE3V1UD00
(11) Caution on rewriting cycles in high-accuracy T-PWM mode
In high-accuracy T-PWM mode, setting conditions for the TRnCCR0, TRnDTC0, and TRnDTC1
registers are as follows.
• 3
×
MAX (TRnDTC0, TRnDTC1) + MIN (TRnDTC0, TRnDTC1) < TRnCCR0
0002H < TRnCCR0
≤
FFFEH
• MAX (A, B) indicates the greater value of A and B, and MIN (A, B) indicates the smaller value of
A and B.
Figure 10-70 shows an operation example when the setting range is exceeded.
This example shows the case where the TRnDTC0 register is set out of the range “TRnDTC0
≥
TRnCCR0
−
TRnDTC1”. Though the 16-bit counter executes count-down operation, the count-
down operation is executed from 0000H because no match occurs. In this case, the count opera-
tion continues by loading the TRnDTC0 register setting value. However, no match with TRnCCR0
−
TRnDTC1 occurs in the count-up operation, thus the 16-bit counter overflows. In this case, the
count operation continues by loading the TRnDTC0 register setting value again.
An overflow interrupt (INTTRnOV) occurs when the 16-bit counter loads the TRnDTC0 register
setting value from 0000H or when an overflow occurs at FFFEH, and then the TRnOVF flag is set.
An overflow interrupt (INTTRnOV) does not occur if the TRnCCR0, TRnDTC0, and TRnDTC1 reg-
isters are set correctly, so this can be used for detecting incorrect settings.
Figure 10-70: Operation Example Setting Is Out of Range
FFFEH
0000H
TRnDTC0
TRnCCR0 to
TRnDTC1
16-bit counter
16-bit sub-counter
INTTRnOV
Changed to “TRnDTC0 TRnCCR0
TRnDTC1” (out of settable range)