NEC V850E/PH2, User Manual

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Chapter 11 16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
11.6.6 Free-running mode
The operation timing of the free-running mode is shown below.
The operation for bits TTnCCS1 and TTnCCS0 of register TTnOPT0 is specified.
Figure 11-29: Basic Operation Flow in Free-Running Mode
Remark: n = 0, 1
START
TTnCCS1, TTnCCS0
settings
Initial settings
Clock selection
(TTnCTL0: TTnCKS2 to TTnCKS0)
Free-running mode setting
(TTnCTL1: TTnMD3 to TTnMD0 = 0101)
Match between
TTnCCR1 buffer
and counter
Match between
TTnCCR0 buffer
and counter
TITn0 edge detection
settings
(TTnIS1, TTnIS0)
TTnCCS1 = 0
TTnCCS0 = 0
TTnCCS1 = 0
TTnCCS0 = 0
TTnCCS1 = 1
TTnCCS0 = 1 TTnCCS1 = 1
TTnCCS0 = 1
Timer operation enable
(TTnCE = 1)
Transfer of values of
TTnCCR0 and
TTnCCR1 to TTnCCR0
and TTnCCR1 buffers
Timer operation enable
(TTnCE = 1)
Transfer of value of
TTnCCR1 to TTnCCR1
buffer
Counter overflow
Timer operation enable
(TTnCE = 1)
Transfer of value of
TTnCCR0 to TTnCCR0
buffer
Match between
TTnCCR1 buffer
and counter
TITn0 edge
detection, capture
of counter value
to TTnCCR0
Counter overflow Counter overflow
Counter overflow
Match between
TTnCCR1 buffer
and counter
Timer operation enable
(TTnCE = 1)
TITn1 and TITn0 edge
detection settings
(TTnIS3, TTnIS2)
TITn1 edge
detection, capture
of counter value
to TTnCCR1
TITn0 edge
detection, capture
of counter value
to TTnCCR0
TITn1 edge
detection, capture
of counter value
to TTnCCR1
TITn1 edge detection
settings
(TTnIS3, TTnIS2)
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