Mitsubishi Electric MELSEC iQ-R-R00CPU, User Manual

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10 TEST FUNCTION
10.1 External Input/Output Forced On/Off Function
Forced on/off timing
The following table lists the timing to reflect the registered data in the forced on/off registration settings to the input/output
devices or external outputs.
*1 For the precautions for using the direct access device, refer to the following.

Page 156 Precautions
*2 At input/output refresh execution where input/output refresh is registered for each program, and for interrupt programs.
*3 When an output device or external output is specified as a refresh device in multiple CPU refresh and the forced on/off function is
executed, the device is not forcibly turned on or off.
Checking the forced on/off execution status
The execution status of the forced on/off can be checked in the following ways.
■
Engineering tool
The execution status can be checked with the [Update Status] button of the engineering tool. (

Page 152 Operation
method of forced on/off)
■
FUNCTION LED
The FUNCTION LED of the CPU module flashes by registering forced on/off (every 200ms).
The LED indicator follows the status of the external input/output forced on/off function even when the LED
Display Setting has been set and other functions that use the FUNCTION LED are being executed. (

Page 131 LED display setting)
The display status of the FUNCTION LED can be checked with "Module Information List" in the module diagnostics. (

GX
Works3 Operating Manual)
Inputs/outputs for which forced on/off
can be set Reflection timing for the input devices Reflection timing for the output devices or
external outputs
Input/output of the modules mounted on the
base unit • END processing (at input refresh)
• At COM instruction execution (at input refresh)
• At instruction execution using the direct access
input (DX) (LD, LDI, AND, ANI, OR, ORI, LDP,
LDF, ANDP, ANDF, ORP, ORF, LDPI, LDFI,
ANDPI, ANDFI, ORPI, ORFI)
*1
• At execution of the RFS instruction and MTR
instruction
• At execution of instructions used in the interrupt
by the system (UDCNT1, UDCNT2, SPD)
• At program execution
*2
• At execution of the inter-module synchronization
cycle program (I44)
• At execution of the multiple CPU synchronization
program (I45) and non-execution of the multiple
CPU synchronization program (I45) (at END
processing)
*3
• END processing (at output refresh)
• At COM instruction execution (at output refresh)
• At instruction execution using the direct access
output (DY) (OUT, SET, DELTA(P), RST, PLS,
PLF, FF, MC, SFT(P))
*1
• At execution of the RFS instruction and MTR
instruction
• At execution of instructions used in the interrupt
by the system (PLSY, PWM)
• At program execution
*2
• At execution of the inter-module synchronization
cycle program (I44)
Input/output of the CPU module assigned to LX
and LY of the CC-Link IE Controller Network
module or MELSECNET/H module • END processing (at link refresh of the CC-Link IE Controller Network module or MELSECNET/H module)
• At COM instruction execution (at link refresh of the CC-Link IE Controller Network module or
MELSECNET/H module)
• At ZCOM instruction execution (at link refresh of the CC-Link IE Controller Network module or
MELSECNET/H module)
Input/output of the CPU module assigned to RX
and RY of the CC-Link module • END processing (at link refresh)
• At COM instruction execution (at link refresh)
• At ZCOM instruction execution (at link refresh)
Input/output of the CPU module assigned to RX
and RY of the CC-Link IE Field Network module • END processing (at link refresh)
• At COM instruction execution (at link refresh)
• At ZCOM instruction execution (at link refresh)
• At execution of the inter-module synchronization cycle program (I44)
Input/output of the CPU module assigned to RX
and RY of the CC-Link IE Field Network Basic • END processing (at link refresh)
• At COM instruction execution (at link refresh)