Mitsubishi Electric MELSEC iQ-R-R00CPU, User Manual

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16 MULTIPLE CPU SYSTEM FUNCTION
16.5 Multiple CPU Synchronous Interrupt
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16
Execution timing
The multiple CPU synchronous interrupt program (I45) is executed at the timing for the fixed scan communication cycle. The
fixed scan communication cycle can be changed through the fixed scan communication setting. (

Page 302 Fixed scan
communication setting)
It is also possible to perform refresh during the multiple CPU synchronous interrupt program (I45) in
execution. (

Page 305 Communication through refresh)
Multiple interrupt
For the multiple interrupt of the multiple CPU synchronous interrupt program, refer to the multiple interrupt function. (

Page 81 Multiple interrupt function)
Precautions
The precautions for the multiple CPU synchronous interrupt program are mentioned below.
• Create a multiple CPU synchronous interrupt program so that it has the execution processing time shorter than the fixed
scan communication cycle. If the interrupt program has the execution processing time equal to or longer than the cycle, the
multiple CPU synchronous interrupt interval cannot be guaranteed. (
 Page 68 Operation upon occurrence of an
interrupt factor) The execution time of the multiple CPU synchronous interrupt program (I45) can be monitored using the
RAS setting of the CPU parameter. (
 Page 128 Error detection setting)
• To send data successfully in the next fixed scan communication cycle, select "Detect" for "Program Execution Section
Exceed (I45)" in "RAS Setting" of [CPU Parameter]. (

Page 128 Error detection setting) With this setting, when data is
written after the host CPU module starts data transfer in the multiple CPU synchronous interrupt program, SM484
(Execution section excess error flag for multiple CPU synchronization interrupt program) is turned on and the number of
data sending errors in the next cycle is stored in SD484 (Number of execution section excess errors for multiple CPU
synchronization interrupt program). In addition, when the data is written while the data cannot be sent in the fixed scan
communication cycle set in a parameter, an error can be detected. (The CPU module continues its operation.)
(1) CPU No.1 receives send data (A) of CPU No.2 in the next scan.
(2) CPU No.1 receives send data (B) of CPU No.2 after two scans.
(3) SM484 turns on and SD484 counts up because CPU No.2 continuously executes its program even after the start of data communication.
(4) Send data (A) of CPU No.2 is written.
(5) Send data (B) of CPU No.2 is written.
(6) This data is sent in the next scan because it has been written before data update.
(7) This data is sent after two scans because it has been written after data update.
(7) (6)
(4) (5)
(3)
(1)
(2)
Data communication
section by system
Send data of CPU No.2
Fixed scan communication cycle
Multiple CPU synchronous
interrupt program of the
CPU No.1
Multiple CPU synchronous
interrupt program of the
CPU No.2
Fixed scan communication cycle