MIPS MIPS32 74K Series, Programming Manual

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Chapter 2
Programming the MIPS32® 74K™ Core Family, Revision 02.14 21
Initialization and identity
What happens when the CPU is first powered up? These functions are perhaps more often associated with a ROM
monitor than an OS.
2.1 Probing your CPU - Config CP0 registers
The four registers
Config
and
Config1-3
are 32-bit CP0 registers which contain information about the CPU’s capa-
bilities.
Config1-3
are strictly read-only. The few writable fields in
Config
— notably
Config[K0]
— are there for
historic compatibility, and are typically written once soon after bootstrap and never changed again.
The 74K core also defines
Config7
for some implementation-specific settings (which most programmers will never
use).
Broadly speaking the registers have these roles:
While initializing your CPU, you might also want to look at the
EBase
register, which can be used to relocate your
exception entry points: see Figure 5.2 and the text round it.
Table 2.1 Roles of Config registers
Config
A mix of historical and CPU-dependent information, described in Figure 2.1 below. Some
fields are writable.
Config1 Read-only, strictly to the MIPS32 architecture. Config1 shows the primary cache configuration
and basic CPU capabilities, while
Config2
shows information about L2 and L3 caches, if fitted
(the L2 and the L3 cache is unavailable in 74K family cores). Shown in Figure 2.2 and Figure
2.3 below.
Config2
Config3
Read-only, strictly to Release 2 of the [MIPS32] architecture.
More CPU capability information.
Config6 Provides information about the presence of optional extensions to the base MIPS32 architec-
ture in addition to those specified in
Config2
and
Config3
.
Config7
74K-core-specific, with both read-only and writable fields. It’s a strong convention that the
writable fields should default to “expected” behavior, so beginners may simply leave these
fields alone. The fields are described later, in
Section B.2.1 “The Config7 register” .