MIPS MIPS32 74K Series, Programming Manual

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74K™ core features for debug and profiling
103 Programming the MIPS32® 74K™ Core Family, Revision 02.14
• You can configure your hardware to take periodic snapshots of the address of the currently-executing instruction
(“PC sampling”) and make those samples available to an EJTAG probe, as described in the next section.
On these foundations powerful debug facilities can be built.
The multi-vendor [EJTAG] specification has many independent options, but MIPS Technologies cores tend to have
fewer options and to implement the bulk of the EJTAG specification. The 74K core can be configured by your SoC
designer with either four instruction breakpoints (or none), and with two data breakpoints (or none). It is also optional
whether the dedicated debug-interrupt signal
DINT
is available in your SoC.
8.1.1 Debug communications through JTAG
The chip’s JTAG pins give an external probe access to a special registers inside the core. The JTAG standard defines a
serial protocol which lets the probe run one of a number of JTAG “instructions”, each of which typically reads/writes
one of a number of registers. EJTAG’s instructions are shown in
Table 8.1 .
8.1.2 Debug mode
A special CPU state; the CPU goes into debug mode when it takes any debug exception - which can be caused by an
sdbbp
instruction, a hit on an EJTAG breakpoint register, from the external “debug interrupt” signal DINT , or single-
stepping (the latter is peculiar and described briefly below). Debug mode state is visible as
Debug[DM]
(see Figure 8.1
below). Debug mode (like exception mode, which is similar) disables all normal interrupts. The address map changes
in debug mode to give you access to the “dseg” region, described below. Quite a lot of exceptions just won’t happen
in debug mode: those which do, run peculiarly - see the relevant paragraphs in
Section 8.1.2, "Debug mode" .
Table 8.1 JTAG instructions for the EJTAG unit
JTAG “Instruction” Description
IDCODE
Reads out the MIPS core and revision - not very interesting for software, not described
further here.
ImpCode Reads bit-field showing what EJTAG options are implemented - see Figure 8.5 below.
EJTAG_ADDRESS (read/write) together, allow the probe to respond to instruction fetches and data reads/
writes in the magic “dmseg” region described in
Section 8.1.5, "The “dseg” memory
decode region" .
EJTAG_DATA
EJTAG_CONTROL Package of flags and control fields for the probe to read and write; see Figure 8.7 below.
EJTAGBOOT The “EJTAGBOOT” instruction causes the next CPU reset to lead to CPU booting from
probe; see description of the
EJTAG_CONTROL bits ProbEn , ProbTrap and
EjtagBrk
in the notes to Figure 8.7 .
The “NORMALBOOT” instruction reverts to the normal CPU bootstrap.
NORMALBOOT
FASTDATA
Special access used to accelerate multi-word data transfers with probe. The probe reads/
writes the 33-bit register formed of a “fast” bit with
EJTAG_DATA
.
FDC Fast Debug Channel. Another accelerated data transfer. This one is accessible by non-
debug mode software and it includes FIFOs to separate the software views from the
physical data transfer, making it non-blocking. See
Section 8.1.10 “Fast Debug
Channel”
TCBCONTROLA
Access registers used to control “PDtrace” instruction trace output, if available.
TCBCONTROLB
TCBCONTROLC
TCBCONTROLD
TCBCONTROLE
PCSAMPLE
Access register which holds PC sample value, see Section 8.1.14, "PC Sampling with
EJTAG" .