MIPS MIPS32 74K Series, Programming Manual

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125 Programming the MIPS32® 74K™ Core Family, Revision 02.14
TraceControl2[TBI,TBU] : best considered together, these read-only bits tell you whether there is an on-chip trace mem-
ory, on-probe trace memory, or both - and which is currently in use.
TraceControl2[SyP] : read-only field which lets you know how often the trace unit sends a complete PC address for syn-
chronization purposes, counted in CPU pipeline clock cycles. The period is
2
(SyP + 5)
. Valid periods are
2
5
to
2
12
.
TraceControl2[SyPExt] : This is an extension to the SyP. It is useful when a higher number of cycles is desired between
synchronization events. The same formula applies as that described above, except that it applies to the juxtaposition
of SyPExt and SyP. The period is
2
(SyPExt ,SyP + 5)
. Valid periods are
2
5
to
2
31
. If the user tries to specify a
period above
2
31
, the behavior is unpredictable.
TraceControl3[ FDT]: set to 1 to indicate that Filtered Data Trace is enabled
TraceControl3[ TRPAD]: read-only bit that is loaded from TCBControlB
TRPAD
.
TraceControl3[ TrIDLE] :read-only bit that is set by the hardware to indicate that the trace unit is not processing any data.
This is especially useful when switching control from hardware to software and vice-versa. After turning trace off
(recommended to turn
TraceControll[ON] , TCBCONTROLA[ON] , and TCBCONTROLB[EN] off) , this bit should be
queried and if the trace unit is idle, then it is safe to change the trace control settings. After changing the settings,
trace can be turned back on, and tracing resumes cleanly with the new control.
The rest of the bits in TraceControl3 enable and control performance counter tracing.
8.2.3 JTAG triggers and local control through TraceIBPC/TraceDBPC
Recent revisions of the PDtrace specification have defined much finer controls on tracing. In particular, you can now
trace only cycles matching some “breakpoint” criteria, and there is a two-stage process where cycles are traced only
after an “arm” condition is detected. The new fields are shown in
Figure 8.21
In either
TraceIBPC
or
TraceDBPC
:
PCT
: set to 1 and a performance counter trigger signal is generated when an EJTAG breakpoint match occurs.
IE,DE
: master 1-to-enable bit for triggers from EJTAG instruction and data breakpoints respectively.
ATE
: Read-only bit which lets you know whether the additional trigger controls such as ARM, DISARM, and data-qual-
ified tracing (introduced in v4.00 of the PDtrace specification) are available - which they may be on the 74K core.
This bit is deprecated and reads as zero.
TBI TBU On-chip or probe trace memory?
0 0
only on-chip memory available
0 1
only probe memory available
1 0
Both available, currently using on-chip
1 1
Both available, currently using probe
Figure 8.21
Fields in the TraceIBPC/TraceDBPC registers
31 30 29 28 27 26 24 23 21 20 18 17 15 14 12 11 9 8 6 5 3 2 0
TraceIBPC
0 PCT
IE
ATE
IBPC3 IBPC2 IBPC1 IBPC0
TraceDBPC
DE DBPC1 DBPC0