MIPS MIPS32 74K Series, Programming Manual

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4.12 Multiply/divide unit and timings
Programming the MIPS32® 74K™ Core Family, Revision 02.14 66
No multiply/divide operation ever produces an exception - even divide-by-zero is silent — compilers typically insert
explicit check code where it’s required.
Timing varies. Multiply-accumulate instructions (there are many different flavors of MAC in the DSP ASE) have
been pipelined and tuned to achieve a 1-instruction-per-clock repeat rate, even for sequences of instructions targeting
the same accumulator. But because that requires a relatively long pipeline, multiply/divide unit instructions which
produce a result in a GP register are relatively “slow”: for example, an instruction consuming the register value from
a
mflo
will not be issued until at least 7 cycles after the
mflo
.
Divides are much slower again. All the timings are summarized in Table 4.3 .
What that means is that in an instruction sequence like:
mult $1, $2
mflo $3
addu $2, $3, 1
The
mflo
will be issued 4 cycles after the
mult
, and the
addu
will go at least 2 cycles after the
mflo
. The execution
unit may (or may not) be able to find other instructions to keep it busy, but each trip through that code sequence will
take a minimum of 9 cycles.