The MIPS32® DSP ASE
97
Programming the MIPS32® 74K™ Core Family, Revision 02.14
addsc rd,rs,rt
Add setting carry, then add with carry. The carry bit is kept in
DSPControl[c]
. So to add
the 64-bit values in registers
yhi
/
ylo
,
zhi
/
zlo
to produce a 64-bit value in
xhi
/
xlo
, just do:
addsc xlo, ylo, zlo; addwc xhi, yhi, zhi
addwc rd,rs,rt
addu.qb rd,rs,rt
4
×
SIMD QBYTE addition, without and with SATUBYTE saturation.
addu_s.qb rd,rs,rt
bitrev rd,rt
Delivers the bit-reversal of the low 16 bits of the input (result has high half zero).
bposge32 offset
Branch if
DSPControl[pos]
>=32. Like most branch instruction, it has a 16-bit “PC-rel-
ative” target encoding.
cmp.eq.ph rs,rt
Signed compare of both halves of two paired-half (“PH”) values. Results are written into
DSPControl[ccond1-0]
for high and low halves respectively (1 for true, 0 for false).
A signed compare works for both Q15 or signed 16-bit values.
cmp.le.ph rs,rt
cmp.lt.ph rs,rt
cmpgu.eq.qb rd,rs,rt
Unsigned simultaneous compare of all four bytes in quad-byte values. The four result
bits are written into the four LS bits of general register
rd
.
cmpgu.le.qb rd,rs,rt
cmpgu.lt.qb rd,rs,rt
cmpu.eq.qb rs,rt
Unsigned simultaneous compare of all four bytes in quad-byte values. The four result
bits are written into register
DSPControl[cond3-0]
.
cmpu.le.qb rs,rt
cmpu.lt.qb rs,rt
dpaq_s.w.ph ac,rs,rt
“Dot product and accumulate”, with Q31 saturation of each multiply result:
ph rs,rt; ac += SAT31(rs.h0*rt.h0 + rs.h1*rt.h1);
The accumulator is effectively used as a Q32.31 fraction.
dpaq_sa.l.w ac,rs,rt
Q31 saturated multiply-accumulate
dpau.h.qbl
qb rs, rt;
ac += rs.b3*rt.b3 + rs.b2*rt.b2;
Dot-product and accumulate of quad-byte values ("l" for left, because these are the
higher bit-numbered bytes in the 32-bit register).
Not a fractional computation, just unsigned 8-bit integers.
dpau.h.qbr
Then for the lower bit-numbered bytes:
qb rs, rt;
ac += rs.b1*rt.b1 + rs.b0*rt.b0;
dpsq_s.w.ph ac,rs,rt
Paired-half fractional “dot product and subtract from accumulator”
ph rs, rt;
q32_31 ac;
ac -= SAT31(rs.h1*rt.h1 + rs.h0*rt.h0);
dpsq_sa.l.w ac,rs,rt
Q31 saturated fractional-multiply, then subtract from accumulator:
q31 rs, rt; q32_31 ac;
ac -= SAT31(rs*rt);
QB format dot-product and subtract from accumulator. This is an integer (not fractional)
multiplication and comes in “left” and “right” (higher/lower-bit numbered pair) versions:
dpsu.h.qbl ac,rs,rt
qb rs,rt;
ac -= rs.b3*rt.b3 + rs.b2*rt.b2;
dpsu.h.qbr ac,rs,rt
qb rs,rt;
ac -= rs.b1*rt.b1 + rs.b0*rt.b0;
extp rt,ac,size
Extract bitfield from an accumulator to register. The length of the field (number of bits)
can be an immediate constant or can be provided by a second source register (in the
v
variants).
The field position, though, comes from
DSPControl[pos]
, which marks the highest-
numbered bit of the field (note that the MIPS32 standard bitfield extract instructions
specify the lowest bit number in the field). In the
dp
variants like
extpdp
/
extpdpv
,
DSPControl[pos]
is auto-decremented by the length of the field extracted, which is use-
ful when unpacking the accumulator into a series of fields.
extpdp rt,ac,size
extpdpv rt,ac,rs
extpv rt,ac,rs
Table 7.2 DSP instructions in alphabetical order
Instruction
Description
Summary of Contents for MIPS32 74K Series
Page 1: ...Document Number MD00541 Revision 02 14 March 30 2011 Programming the MIPS32 74K Core Family...
Page 10: ...Programming the MIPS32 74K Core Family Revision 02 14 10...
Page 54: ...3 8 The TLB and translation Programming the MIPS32 74K Core Family Revision 02 14 54...
Page 83: ......
Page 101: ...The MIPS32 DSP ASE 101 Programming the MIPS32 74K Core Family Revision 02 14...
Page 134: ...8 4 Performance counters Programming the MIPS32 74K Core Family Revision 02 14 134...