MIPS MIPS32 74K Series, Programming Manual

Page: 144 / 156

B.1 Miscellaneous CP0 register descriptions
Programming the MIPS32® 74K™ Core Family, Revision 02.14 144
The CPU is in EIC mode if
Config3[VEIC]
(indicating the hardware is EIC-compliant), and software has set
Cause[IV]
to enable vectored interrupts. In that case this field is interpreted as an unsigned binary number, and is a
snapshot of the value of the “interrupt priority level” (IPL) supplied by the interrupt controller. The snapshot is from
the time when the CPU decided to take the interrupt exception.
When the presented IPL is higher than the current interrupt priority level held in
Status[RIPL]
, the CPU takes an
interrupt. A zero level on the core inputs indicates no interrupt request.
IP1-0
are writable, and in fact always just reflect the value written here. They act as software interrupt bits masked by
Status[IM1-0]
regardless of the interrupt mode.
Cause[ExcCode]
: what caused that last exception. Lots of values :
Table B.5 Values found in Cause[ExcCode]
Val Code What just happened?
0
Int
Interrupt
1
Mod
Store, but page marked as read-only in the TLB
2
TLBL
Load or fetch, but page marked as invalid in the TLB
3
TLBS
Store, but page marked as invalid in the TLB
4
AdEL
Address error on load/fetch or store respectively. Address is either wrongly aligned, or a privilege viola-
tion.
5
AdES
6
IBE
Bus error signaled on instruction fetch
7
DBE
Bus error signaled on load/store (imprecise)
8
Sys
System call, ie
syscall
instruction executed.
9
Bp
Breakpoint, ie
break
instruction executed.
10
RI
Instruction code not recognized (or not legal)
11
CpU
Instruction code was for a co-processor which is not enabled in
Status[CU3-0]
.
12
Ov
Overflow from a trapping variant of integer arithmetic instructions.
13
Tr
Condition met on one of the conditional trap instructions
teq
etc.
14
-
Reserved
15
FPE
Floating point unit exception — more details in the FPU control/status registers.
16-17
-
Available for implementation dependent use
18
C2E
Reserved for precise Coprocessor 2 exceptions
19-21
-
Reserved
22
MDMX
Tried to run an MDMX instruction but
Status[MX]
wasn’t set (most likely, the CPU doesn’t support the
MDMX ASE)
23
WATCH
Instruction or data reference matched a watchpoint
24
MCheck
“Machine check” — second valid TLB entry mapping same virtual address.
25
Thread
Thread-related exception, only for CPUs supporting the MIPS MT ASE.
26
-
Reserved (some kind of thread exception for a MT CPU).
27-29
-
Reserved
30
CacheErr
Parity/ECC error somewhere in the core, on either instruction fetch, load or cache refill. In fact you never
see this value in
Cause[ExcCode]
; but some of the codes in this table including this one can be visible in
the “debug mode” of the EJTAG debug unit — see and in particular the notes on the Debug register.