MIPS MIPS32 74K Series, Programming Manual

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3.4 Caches
Programming the MIPS32® 74K™ Core Family, Revision 02.14 42
EB : 1 if data and instruction-fetch error reported on same instruction, which is unrecoverable. If so, the rest of the regis-
ter reports on the instruction-fetch error.
On an L2 error: 1 if an error occurred in more than one of the cache's memory arrays if EC is also set— the hardware
manual
[SUM] renames this field as CacheErr[EM] . The rest of the register can only reflect information about one of
the errors: it shows tag errors as highest priority, then data, then way-select.
EF : unrecoverable (fatal) error (other than the EB type above). Some parity errors can be fixed by invalidating the cache
line and relying on good data from memory. But if this bit is set, all is lost... It’s one of the following:
1. Line being displaced from cache (“victim”) has a tag parity error, so we don’t know whether to write it back,
or whether the writeback location (which needs a correct tag) would be correct.
2. The victim’s tag indicates it has been written by the CPU since it was obtained from memory (the line is
“dirty” and needs a write-back), but it has a data parity error.
3. Writeback store miss and CacheErr[EW] error.
4. At least one more cache parity error happened concurrently with or after this one, but before we reached the
relative safety of the cache parity error exception handler.
If the EC bit is set this bit is referring to the errors in L2 (external) cache.
SP: error affecting a scratchpad RAM access, see Section 3.6, "Scratchpad memory/SPRAM" below .
EW : parity error on the “dirty” (cache modified) or way-selection bits. This means loss of LRU information, which —
most of the time — is recoverable.
Way : the way-number of the cache entry where the error occurred. Caution: for the L1 caches (which are no more than
4-way set associative) this is a two-bit field. But an L2 cache might be more highly set-associative, and then this field
grows down. In particular, MIPS’ (possibly 8-way set associative) L2 cache uses a 3-bit
Way field as shown.
DR : A 1 bit indicates that the reported error affected the cache line "dirty" bits.
Index : the index (within the cache way) of the cache entry where the error occurred... except that the low bits are not
meaningful. The index is aligned as if it’s a byte address, which is good because that’s what Index-type
cache
instructions need. It resolves the failing doubleword for a data error, or just the failing line for a tag error. We’ve
shown a 14-bit field, because that’s large enough to provide the index for the 74K core’s largest configurable (4 ways
by 16KB) L1 cache option.
Two other fields are related to the processing of cache errors. Other implementations have laid claim to all of the bits
in this register, so these bits were relegated to the
ErrCtl register. The FE and SE bits in that register are used to detect
nested cache errors and are described in the next section.
If you want to study this error further, you’ll probably use an index-type
cache
instruction to read out the tags and/
or data. The cache instruction’s “index” needs the way-number bits added to CacheErr[Index] ’s contents; see Figure
3.1 and its notes above for how to do that.
3.4.17 ErrCtl register
This register has two distinct roles. It contains “mode bits” which provide different views of the TagLo registers when
they’re used for access to internal memory arrays and cache diagnostics. But it also controls parity protection of the
caches (if it was configured in your core in the first place).