MIPS MIPS32 74K Series, Programming Manual

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CP0 register summary and reference
145 Programming the MIPS32® 74K™ Core Family, Revision 02.14
B.1.4 The EPC register
After any normal exception (debug and error exceptions are different, see
DEPC
and
ErrorEPC
respectively),
EPC
holds the return address.
If the instruction we’d really like to return to is in a branch delay slot,
EPC
points to the branch instruction and
Cause[BD]
will be set. All MIPS branch instructions may be re-executed successfully, so returning to the branch is
the right thing to do in this case.
B.1.5 Count and Compare
These two 32-bit registers form a useful and flexible timer. Count just counts. For the 74K core, that’s usually once
every two clocks. But you should not rely on that: software should discover how fast
Count
counts by reading the
“hardware register” called “CCRes”, see Section 4.1, "User-mode accessible “Hardware registers”" .
You can write Count to set a value in it, but it’s generally more valuable for an OS to leave it as a free-running counter.
When the value of Count coincides with the value in Compare , an interrupt is raised. The interrupt is cleared every
time Compare is written. This is handy:
• For a periodic interrupt, simply advance Compare by a fixed amount each time (and check for the possibility that
Count has overrun it).
• To set a timer for some point in the future, just set Compare to an increment more than the current value of
Count .
The timer interrupt is implemented as an output signal at the core interface; but it’s conventional (well, pretty compul-
sory if you want OS’ to work) to return it to the same VPE on an interrupt line - see notes on
IntCtl[IPTI] below Figure
5.1 . However, if you have an “EIC” interrupt controller (see Section 5.2, "MIPS32® Architecture Release 2 -
enhanced interrupt system(s)" ) you’ll need to send the timer interrupt all the way out to the interrupt controller and
back.
B.2 Registers for CPU Configuration
B.2.1 The Config7 register
Config7
is for implementation-specific fields. A few fields may need to be set to match the hardware configuration of
your system: the rest are typically for diagnostics and test, default to safe values on power up, and are best left alone
otherwise. If you are using these registers, you probably need to consult the core hardware bible, the
[SUM] . Much of
Config7
will be familiar to test-and-diagnostic workers who’ve worked on MIPS Technologies’ 24K or 34K core
families.
31
-
Reserved
Table B.5 Values found in Cause[ExcCode]
Val Code What just happened?