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3.8 The TLB and translation

Programming the MIPS32® 74K™ Core Family, Revision 02.14

PageMask[Mask]

: acts as a kind of backward mask, in that a 1 bit means "don’t compare this address bit when matching

this address". However, only a restricted range of

PageMask

values are legal (that’s with "1"s filling the

PageMask[Mask]

field from low bits upward, two at a time):

Note that the uTLBs handle only 4Kbyte and 16Kbyte page sizes; other page sizes are down-converted to 4Kbyte or
16Kbyte as they are referenced. For other page sizes this may cause an unexpectedly high rate of uTLB misses, which
could be noticeable in unusual circumstances.

Then moving our attention to the output side, the two

EntryLo0-1

are identical in format as shown in

Figure 3.13

EntryLo0-1

PFN

: the "physical frame number" - traditional OS name for the high-order bits of the physical address. 24 bits of

PFN

together with 12 bits of in-page address make up a 36-bit physical address; but the 74K core has a 32-bit physical
address bus, and does not implement the four highest bits (which always read back as zero).

: a code indicating how to cache data in this page - pages can be marked uncacheable and various flavours of cache-

able. The codes here are shared with those used in CP0 registers for the cacheability of fixed address regions: see

Table 3.3

Section 3.4.2, "Cacheability options" on page 33

: the "dirty" flag. In hardware terms it’s just a write-enable (when it’s 0 you can’t do a store using addresses translated

here, you’ll get an exception instead). However, software can use it to track pages which have been written to; when
you first map a page you leave this bit clear, and then a first write causes an exception which you note somewhere in
the OS’ memory management tables (and of course remember to set the bit).

: the "valid" flag. You’d think it doesn’t make much sense - why load an entry if it’s not valid? But this is very helpful

so you can make just one of a pair of pages valid.

: the "global" bit. This really belongs to the input side, and there aren’t really two independent values for it. So you

should always make sure you set

EntryLo0[G]

and

EntryLo1[G}

the same.

3.8.5 TLB initialization and duplicate entries

TLB entries come up to random values on power-up, and must be initialized by hardware before use. Generally, early
bootstrap software should go through setting each entry to a harmless “invalid” value.

Since the TLB is a fully-associative array and entries are written by index, it’s possible to load duplicate entries - two
or more entries which match the same virtual address/ASID. In older MIPS CPUs it was essential to avoid duplicate
entries - even duplicate entries where all the entries are marked “invalid”. Some designs could even suffer hardware

PageMask

Size of each output page

PageMask

Size of each output page

0x0000.0000

4Kbytes

0x007F.E000

4Mbytes

0x0000.6000

16Kbytes

0x01FF.E000

16Mbytes