MIPS MIPS32 74K Series, Programming Manual

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8.2 PDtrace™ instruction trace facility
Programming the MIPS32® 74K™ Core Family, Revision 02.14 126
IBPC8-0, DBPC8-0 : each three-bit field encodes tracing options independently, for up to nine EJTAG I- and D-side
breakpoints (this is generous: your 74K core will typically have no more than 4 I- and 2 D-breakpoints).
Each entry can be set as follows:
However, do TraceIBPC / TraceDBPC exist in your system? They will be there only if you have an EJTAG unit (does
Config1[EP] read 1?), and that unit has at least one breakpoint register - check that at least one of DCR[DB,IB] is set
(as described in).
8.2.4 UserTraceData1 reg and UserTraceData2 reg
Write any 32-bit value you like here and the trace unit will send a “user” record (if only one UserTraceData register
exists, then there are two “types” of user record, and which you output depends on TraceControl[UT] , see above).
However if two UserTraceData registers exist then writing to UserTraceData1 will generate a trace record with type
UT1, and writing to UserTraceData2 will generate a trace record with type UT2. You need to send something your
trace analysis system will understand, of course! Perhaps it’s worth noting that this “user” is local debug software,
and doesn’t mean low-privilege software running in “user mode” - which of course would not be able to access this
register. CP0 access rules apply when writing to this “user” register.
8.2.5 Summary of when trace happens
The many different enable bits which control trace add up to (or strictly “and” up to) a whole bunch of reasons why
you won’t get any trace output. So it may be worth summarizing them here. So:
• If software is in charge (that is, if TraceControl[TS] ==
1
) then:
– TraceControl[On] must be set.
– At least one of the CPU mode filter bits TraceControl[D,E,S,K,U] must be set 1 to trace instructions in debug,
exception, supervisor, kernel or user-mode respectively. Mostly likely either just TraceControl[U] will be set (to
follow just one process in a protected OS), or TraceControl[E,S,K,U] to follow all the software at bare-iron
level (but not to trace EJTAG debug activity);
– Either TraceControl[G] is set (to trace everything regardless of current ASID) or TraceControl[ASID] (as
masked by TraceControl[ASID_M] ) matches the current value of the core-under-test’s EntryHi[ASID] field.
– The signal
PDI_TraceOn
is asserted by the trace block. This will typically be true whenever the probe is
plugged in and connected to software.
– As above there are D,E,S,K,U,G and ASID bits (there isn’t an “ASID_M” in this case) which must be set
appropriately in the JTAG-accessible TCBCONTROLA register, which is not otherwise described here.
Whether JTAG or TraceControl is in charge, then:
xBPC field Description
0
Stop tracing (no effect if off already).
1
Start tracing (no effect if on already).
2
Trace instructions which cause this trigger.