MIPS MIPS32 74K Series, Programming Manual

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MIPS® Architecture quick-reference sheet(s)
153 Programming the MIPS32® 74K™ Core Family, Revision 02.14
• CC (2): user-mode read-only access to the CP0
Count
register, for high-resolution counting. Which wouldn’t be
much good without...
• CCRes (3): which tells you how fast
Count
counts. It’s a divider from the pipeline clock (if the rdhwr instruction
reads a value of “2”, then
Count
increments every 2 cycles, at half the pipeline clock rate).
• UserLocal (29): Scratch register of sorts. The kernel can store a thread specific value such as a thread ID or a
pointer to thread specific storage to the underlying Cop0 register and user mode programs can read it via
rdhwr
C.3 FPU changes in Release 2 of the MIPS32® Architecture
The main change is that a 32-bit CPU (like the 74K core) can now be paired with a 64-bit floating point unit. The FPU
itself is compatible with the description in
[MIPS64V2] .
The only new feature of the instruction set are the
mfhc1
/
mthc1
instructions described in Section C.2, "Release 2 of
the MIPS32® Architecture - new instructions" .
But it’s worth stressing that the floating point unit implements 64-bit load and store instructions. The FPU of the 74K
core is described in
Chapter 6, “Floating point unit” on page 77 .