MIPS MIPS32 74K Series, Programming Manual

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121 Programming the MIPS32® 74K™ Core Family, Revision 02.14
8.2 PDtrace™ instruction trace facility
An instruction trace is a set of data generated when a program runs which allows you to recreate the sequence of
instructions executed, possibly with additional information included about data values. Instruction traces rapidly
become enormous, and are typically generated in some kind of abbreviated form, which may be reconstructed by
software which is in possession of a copy of the binary code of your system.
74K family cores can be configured with PDtrace logic, which provides a non-intrusive way of finding out what
instructions your CPU ran. If your system includes PDtrace logic,
Config3[TL] will read 1.
With a very high-speed CPU like the 74K core this is challenging, because you need to send data so fast. The PDtrace
system deals with this by:
• Compressing the trace: a software tool in possession of the binary of your program can predict where execution
will go next, following sequential instructions and fixed branches. To trace your program it needs only to know
whether conditional branches were taken, and the destination of computed branches like jump-register.
• Switching the trace on and off: the 74K core can be configured with up to 8 “trace triggers”, allowing you to start
and stop tracing based on EJTAG breakpoint matches: see
Section 8.1.11, "EJTAG breakpoint registers" above
and Table 8.21 below.
• High-speed connection to a debug/trace probe: optional. But if fitted, it uses advanced signalling techniques to
get trace data from the CPU core, out of dedicated package pins to a probe. Good probes have generous amounts
of high-speed memory to store long traces.
TraceControl2[ValidModes,TBI,TBU] (described below at Figure 7-10 and following) tell you whether you have
such a connection available on your core. You’ll have to ask the hardware engineers whether they brought out the
connector, of course.
• Very high-speed on-chip trace memory: if fitted, you may find between 256bytes and 8Mbytes of trace memory
in your system (larger than a few Kbytes is unlikely). Again, see
TraceControl2[ValidModes,TBI,TBU] to find out
what facilities you have.
• Option to slow the CPU to match the tracing speed: when you really, really need a full trace, and are prepared to
slow down your program if necessary to wait while the trace information is sent to the probe. This is controlled
by
TraceControl[IO] , see below.
• Software access to on-chip trace memory : A new mechanism is provided to allow software to read the on-chip
trace memory. This is achieved by mapping all the TCB registers to drseg.
In practice the PDtrace logic depends on the existence of an EJTAG unit (described in the previous section) and an
enhanced EJTAG probe. To benefit from on-probe trace memory, the probe will need to attach to PDtrace-specific
signals.
This manual describes only the lowest-level building blocks as visible to software. For real hardware information
refer to
[PDTRACETCB] ; for guidance about how to use the PDtrace facilities for software development see
[PDTRACEUSAGE] . To use PDtrace facilities, you’ll have to read the software manuals which come with a probe.
8.2.1 74K core-specific fields in PDtrace™ JTAG-accessible registers
The PDtrace system is controlled by the JTAG-accessible registers TCBCONTROLA, TCBCONTROLB, TCBCON-
TROLC, TCBCONTROLD, and TCBCONTROLE. Normally they are not visible to software running on the CPU,