74K™ core features for debug and profiling
115
Programming the MIPS32® 74K™ Core Family, Revision 02.14
Where:
Tx/RxCount
: Optional fields indicating how many FIFO entries are in use. These fields are not implemented and will
read as 0
RxChan
: Channel Identifier for the receive data at the head of the RxFIFO. Not meaningful if
RxE
==1
RxE/RxF/TxE/TxF:
Status of each FIFO. Each one can be either Empty, Full, or somewhere in the middle, in which case
neither E nor F would be set.
TxF
must be checked prior to attempting a write to the transmit FIFO
RxE
must be checked prior to attempting a read from the receive FIFO
The other two status bits would not generally be as useful, but are provided for symmetry
The
FDRX
register is a read-only register that returns the top entry in the receive FIFO. It is undefined if
FDSTAT[RxE]
==1, so that register should be checked prior to reading. That check will also return the ChannelID so
you know what type of data this is.
Figure 8.12 Fields in the FDC Receive (FDRX) Register
The
FDTXn
registers are 16 write-only registers that write into the bottom entry in the transmit FIFO. The 16 copies
provide the means for selecting a ChannelID for the write data. The address used for the write is decoded into the 4-
bit ChannelID and written into the FIFO with the data. Results are undefined if
FDSTAT[TxF]
==1, so that register
should be checked prior to writing data.
Figure 8.13 Fields in the FDC Transmit (FDTXn) Registers
8.1.11 EJTAG breakpoint registers
It’s optional whether the 74K core has EJTAG breakpoint registers. But if it has instruction breakpoints, it has four of
them; and if it has data breakpoints, it has two. The breakpoints:
•
Work only on virtual addresses, not physical addresses. However, you can restrict the breakpoint to a single
address space by specifying an “ASID” value to match. Debuggers will need the co-operation of the OS to get
this right.
•
Use a bit-wise address mask to permit a degree of fuzzy matching.
•
On the data side, you can break only when a particular value is loaded or stored. However, such breakpoints are
imprecise in a CPU like the 74K core - see
Section 8.1.13, "Imprecise debug breaks"
below.
There are instruction-side and data-side breakpoint status registers (they’re located in “drseg”, accessible only when
in debug mode, and their addresses are in
Section 8.2, "EJTAG debug memory region map (“dseg”)"
.) They’re called
IBS
and
DBS
. The latter has, in theory, two extra fields (bits 29-28) used to flag implementations which can’t do a
load/store break conditional on the data value. However, MIPS cores with hardware breakpoints always include the
value check, so these bits read zero anyway. So the registers are as shown in
31
0
RxData
31
0
TxData
Summary of Contents for MIPS32 74K Series
Page 1: ...Document Number MD00541 Revision 02 14 March 30 2011 Programming the MIPS32 74K Core Family...
Page 10: ...Programming the MIPS32 74K Core Family Revision 02 14 10...
Page 54: ...3 8 The TLB and translation Programming the MIPS32 74K Core Family Revision 02 14 54...
Page 83: ......
Page 101: ...The MIPS32 DSP ASE 101 Programming the MIPS32 74K Core Family Revision 02 14...
Page 134: ...8 4 Performance counters Programming the MIPS32 74K Core Family Revision 02 14 134...