MIPS MIPS32 74K Series, Programming Manual

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Initialization and identity
23 Programming the MIPS32® 74K™ Core Family, Revision 02.14
BM
: read-only - tells you whether your bus uses sequential or sub-block burst order; set by hardware to match your sys-
tem controller.
BE
: reads 1 for big-endian, 0 for little-endian.
AT
: MIPS32 or MIPS64 compliance On 74K family cores it will read “0”, but the possible values are:
AR
: Architecture revision level. On 74K family cores it will read “1”, denoting release 2 of the MIPS32 specification.
MT
: MMU type (all MIPS Technologies cores may be configured as type 1 or 3):
VI
: 1 if the L1 I-cache is virtual (both indexed and tagged using virtual address). No contemporary MIPS Technologies
core has a virtual I-cache.
K0
: as described in the notes above on Config[K23] etc, this field determines the cacheing behaviour of the fixed kseg0
memory region .
2.1.2 The Config1-2 registers
These two read-only registers tell you the size of the TLB, and the size and organization of L1, L2 and L3 caches (a
zero “line size” is used to indicate a cache which isn’t there). They’re best described together.
Config1
has some fields which tell you about the presence of some of the older extensions to the base MIPS32 archi-
tecture are implemented on this core. These bits ran out, and other extensions are noted in
Config3
.
Figure 2.2 Fields in the Config1 Register
Figure 2.3 Fields in the Config2 Register
Config1[M]
: continuation bit, 1 if
Config2
is implemented.
0 MIPS32
1 MIPS64 instruction set but MIPS32 address map
2 MIPS64 instruction set with full address map
0 MIPS32/MIPS64 Release 1
1 MIPS32/MIPS64 Release 2
0 None
1 MIPS32/64 compliant TLB
2 “BAT” type
3 MIPS-standard fixed mapping
31 30 25 24 22 21 19 18 16 15 13 12 10 9 7 6 5 4 3 2 1 0
M MMUSize IS IL IA DS DL DA C2 MD PC WR CA EP FP
1 4 3 4 3 0 1 1 1 1
31 30 28 27 24 23 20 19 16 15 13 12 11 8 7 4 3 0
M TU TS TL TA SU L2B SS SL SA
1 0 0 0 0 0 0