MIPS MIPS32 74K Series, Programming Manual

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Memory map, caching, reads, writes and translation
35 Programming the MIPS32® 74K™ Core Family, Revision 02.14
The
op
field packs together a 2-bit field which selects which cache to work on:
and then adds a 3-bit field which encodes a command to be carried out on the line the instruction selects.
Before we list out the individual commands in Table 3.4 ; the cache commands come in three flavors which differ in
how they pick the cache entry (the “cache line”) they will work on:
• Hit-type cache operation: presents an address (just like a load/store), which is looked up in the cache. If this loca-
tion is in the cache (it “hits”) the cache operation is carried out on the enclosing line. If this location is not in the
cache, nothing happens.
• Address-type cache operation: presents an address of some memory data, which is processed just like a cached
access - if the cache was previously invalid the data is fetched from memory.
• Index-type cache operation: as many low bits of the address as are required are used to select the byte within the
cache line, then the cache line address inside one of the four cache ways, and then the way. You have to know the
size of your cache (discoverable from the
Config1-2 registers, see ) to know exactly where the field boundaries
are, but your address is used something like this:
Beware: the MIPS32 specification leaves CPU designers to choose whether to derive the index from the virtual or
physical address. Don’t leave it to chance: with index-type operations use a kseg0 address, so that the virtual and
physical address are the same (at least apart from some high bits which certainly won’t affect any cache index).
This also avoids a potential pitfall related to cache aliases.
The L1 caches are 4-way set-associative, so data from any given address has four possible cache locations - same
index, different value of the “Way1-0” bits as above.
Don’t define your own C names for cache manipulation operation codes, at least not if you can use a standard header
file from MIPS Technologies on open-source terms: see
[m32c0 h] .
3.4.5 Cache instructions and CP0 cache tag/data registers
MIPS Technologies’ cores use different CP0 registers for cache operations targeted at different caches. That’s already
quite confusing, but to make it more interesting these registers have somehow got different names — those used here
0 L1 I-cache
1 L1 D-cache
2 reserved for L3 cache
3 L2 cache
31 5 4 0
Unused Way1-0 Index byte-within-line