MIPS MIPS32 74K Series, Programming Manual

Page: 40 / 156

3.4 Caches
Programming the MIPS32® 74K™ Core Family, Revision 02.14 40
PTagLo : the cache address tag - a physical address because the 74K core’s caches are physically tagged. It holds bits
31–12 of the physical address - the low 12 bits of the address are implied by the position of the data in the cache.
×
: a field not described for the 74K core but which might not always read zero.
V : 1 when this cache line is valid.
E : always 0
L : 1 when this cache line is locked, see Section 3.4.10, "Cache locking" .
P0 : parity bit for tag fields other than the TagLo[D] bit, which is actually held separately in the "way-select" RAM.
When you use the TagLo register to write a cache tag with
cache IndexStoreTag
the TagLo[P] : bit is generally
not used - instead the hardware puts together your other fields and ensures it writes correct parity. However, it is pos-
sible to force parity to exactly this value by first setting
ErrCtl[PO] .
3.4.12 L23TagLo Regiser
This register in the 74K core is implemented to support access to external L2 cache tags via
cache
instructions. The
definition of the fields of this 32 bit register are defined by the SoC designer. Refer to the section on L2 Transactions
in the document ““MIPS32® 74K
CoreTrade
Processor core Family Integrator’s Guide, MD00499” for further informa-
tion on using this register.
Figure 3.3 L23TagLo Register Format
3.4.13 L23DataLo Register
On 74K family cores, test software can read or write cache data using a
cache
index load/store data instruction.
Which word of the cache line is transferred depends on the low address fed to the
cache
instruction.
Figure 3.4 L23DataLo Register Format
3.4.14 L23DataHi Register
On 74K family cores, test software can read or write cache data using a
cache
index load/store data instruction.
Which word of the cache line is transferred depends on the low address fed to the
cache
instruction.
31 0
DATA
31 0
DATA
Table 3.5 L23DataLo Register Field Description
Fields
Description
Read /
Write Reset State Name Bit(s)
DATA 31:0 Low-order data read from the cache data array. R/W Undefined