MIPS MIPS32 74K Series, Programming Manual

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2.1 Probing your CPU - Config CP0 registers
Programming the MIPS32® 74K™ Core Family, Revision 02.14 22
2.1.1 The Config register
Figure 2.1 Fields in the Config Register
In Figure 2.1 :
M : reads 1 if Config1 is available (it always is).
K23, KU, K0 : set the cacheability attributes of chunks of the memory map by writing these fields. All share a 3-bit
encoding with the cacheability field found in TLB entries, which is described in Table 3.3 in Section
3.4.2 “Cacheability options” .
Config[K0] sets the cacheability of kseg0, but it would be very unusual to make that anything other than cacheable
(on different, cache-coherent CPUs, it may want to be set to cacheable-coherent). The power-on value of this standard
field is not mandated by the
[MIPS32] architecture; but the 74K core follows the recommendation to set it to "
2
",
making "kseg0" uncached. That can be surprising; early system initialization software typically re-writes it to "
3
" in
order that kseg0 will be cached, as expected.
If your
74K
core-based system uses fixed mapping instead of having a TLB, Config[K23] is for program addresses
0xC000.0000-0xFFFF.FFFF (the “kseg2” and “kseg3” areas), while Config[KU] is for program addresses
0x0000.0000-0x7FFF.FFFF (the “kuseg” area). If you have a TLB, these regions are mapped and these fields are
unused (write only zeroes to them).
ISP, DSP : read 1 if I-side and/or D-side scratchpad (SPRAM) is fitted, see Section 3.6, "Scratchpad memory/
SPRAM" .
(Don’t confuse this with the MIPS DSP ASE, whose presence is indicated by Config3[DDSP] .)
UDI : reads 1 if your core implements user-defined "CorExtend" instructions. “CorExtend” is available on cores whose
name ends in "Pro".
SB : read-only "SimpleBE" bus mode indicator. If set, means that this core will only do simple partial-word transfers on
its OCP interface; that is, the only partial-word transfers will be byte, aligned half-word and aligned word.
If zero, it may generate partial-word transfers with an arbitrary set of bytes enabled (which some memory controllers
may not like).
WC: Warning: this is a diagnostic/test field, not intended for customer use, and may vanish without notice from a
future version of the core.
Set this 1 to make the Config1[IS] and Config1[DS] fields writable, which allows you to reduce the number of avail-
able L1 I- and D-cache ``sets per way'', and shrink the usable cache size. You'd never want to do this in a real system,
but it is conceivable it might be useful for debug or performance analysis. If you have an L2 cache configured, then
this makes
Config2[SS] writable in the same way.
MM : writable: set 1 if you want writes resulting from separate store instructions in write-through mode merged into a
single (possibly burst) transaction at the interface. This has no affect on cache writebacks (which are always whole
blocks together) or uncached writes (which are never merged).
31 30 28 27 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 9 7 6 4 3 2 0
M K23 KU ISP DSP UDI SB 0 WC MM 0 BM BE AT AR MT 0 VI K0
1 2 2 0 1 0 1 0 2