MIPS MIPS32 74K Series, Programming Manual

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8.1 EJTAG on-chip debug unit
Programming the MIPS32® 74K™ Core Family, Revision 02.14 110
8.1.8 The DebugVectorAddr memory-mapped register
This is another memory-mapped EJTAG register . It’s found in “drseg” at location 0xFF30.0020 as shown in Table
8.2 (but only accessible if the CPU is in debug mode). The fields are in Figure 8.5 :
If enabled via the
RdVec
bit in the
DCR
, this register will control the address used for debug exceptions when a
debug probe is not handling them. By default, the exception handler is located in the boot ROM. If the debugger is
allowed some space in RAM, it can both customize the debug handler and execute faster than from ROM. You can
even make the handler cacheable to speed it up further - of course with the penalty of altering the cache behavior of
the program you are debugging. In some cases, that trade-off may be useful
Figure 8.5 Fields in the memory-mapped DCR (debug control) register
Where:
DebugVectorOffset
: Specify the intermediate bits of the desired debug exception vector. The upper bits of the vector are
fixed to restrict it to kseg0 or kseg1. The lower bits of the vector are fixed to save some hardware costs for no real loss
in functionality.
ISA : In cores with the microMIPS ISA, this bit can specify which ISA the exception handler is built in. This is tied to 0
on this core as the MIPS16 ASE does not have the privledged operations that would make it useful as an exception
handler.
8.1.9 JTAG-accessible registers
We’re wandering away from what is relevant to software here: these registers are available for read and write only by
the probe, and are not software-accessible.
But you can’t really understand the EJTAG unit without knowing what dials, knobs and switches are available to the
probe, so it seems easier to give a little too much information.
First of all there are two informational fields provided to the probe,
IDCODE
(just reflects some inputs brought in to
the core by the SoC team, not very interesting) and the
Implementation Register
; then there’s the main CPU interac-
tion control/status register
EJTAG_CONTROL
( Figure 8.7 ).
Figure 8.6 IFields in the JTAG-accessible Implementation register
Notes on the
Implementation
register fields:
EJTAGver
: same value (and meaning) as the
Debug[EJTAGver]
field, see the notes on Figure 7-2.
31 30 29 7 6 1 0
10 DebugVectorOffset 0 ISA
31 29 28 25 24 23 21 20 17 16 15 14 13 11 10 1 0
EJTAGver Res DINTsup ASIDsize Res MIPS16 0 NoDMA Type TypeInfo
MIPS32/
64
5
= 5.0 0 see note see note 1 1 0