MIPS MIPS32 74K Series, Programming Manual

Page: 142 / 156

B.1 Miscellaneous CP0 register descriptions
Programming the MIPS32® 74K™ Core Family, Revision 02.14 142
Status[TS]
: Set if software attempts to create a duplicate TLB entry (which will also produce a "machine check" excep-
tion). Can be written back to zero, but never written to 1. The name of the field originated as a "TLB Shutdown" —
historical MIPS CPUs quietly stopped translating addresses when they detected TLB abuse.
Status[SR]
: MIPS32 architecture "soft reset" bit: the 74K core’s interface only supports a full external reset, so this
always reads zero.
Status[NMI]
: (read-only) — non-maskable interrupt shares the "reset" handler code, this field reads 1 when it was a
NMI event which caused it.
Status[IM7-0]
: bitwise interrupt enable for the eight interrupt conditions also visible in
Cause[IP7-0]
, except in the
"EIC" interrupt mode.
EIC mode is activated when
Config3[VEIC]
reads 1, and you set
Cause[IV]
and write a non-zero “vector spacing”
into
IntCtl[VS]
.
In EIC mode
IM7-2
is recycled to become a 6-bit
Status[IPL]
(“interrupt priority level”) field. An interrupt is only
triggered when your interrupt controller presents an interrupt code which is numerically higher than the current value
of
Status[IPL]
.
Status[IM1-0]
always act as bitwise masks for the two software interrupt bits programmable at
Cause[IP1-0]
.
Status[UM,SM]
: execution privilege level — basically user or kernel:
The intermediate “supervisor” privilege level is rarely used: but that’s why this is a 2-bit field.
Regardless of this field, the CPU is forced into kernel mode when either
EXL
or
ERL
is set.
Status[ERL,EXL]
:
EXL
is the regular exception mode bit, set automatically when the CPU takes an exception.
ERL
is
the "error exception mode" bit, and is set following reset, an NMI, or a cache error exception. Either bit forces kernel
mode and disables interrupts.
There are some very special cases where nested exceptions are permitted, so an exception with
EXL
set does several
strange things: a nested TLB Refill exception is sent to the general exception handler (not, as is usual, it’s dedicated
entry point), and on a nested exception
EPC
,
Cause[BD]
and
SRSCtl
are not overwritten. The result, broadly, is that
when you return from the second exception you skip straight back to the code which was running before the first. For
more details see
[SEEMIPSRUN] or the [MIPS32] bible.
The error level has its own return address: when
ERL
is set the
eret
instruction gets its address from
ErrorEPC
, not
EPC
as normal.
Moreover, error level changes the memory map (in support of software fixing up cache errors), recycling kuseg as an
uncached, unmapped window onto 512MB of physical memory.
Table B.4 Encoding privilege level in Status[UM,SM]
UM SM Effect
0 0 kernel
0 1 supervisor
1 0 user