MIPS MIPS32 74K Series, Programming Manual

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3.4 Caches
Programming the MIPS32® 74K™ Core Family, Revision 02.14 34
shows the code values used in EntryLo[C] - the same codes are used in the Config entries used to set the behavior of
regions with fixed mappings (the latter are described in Table 3.2 .)
Some of the undefined cacheability code values are reserved for use in cache-coherent systems.
3.4.3 Uncached accelerated writes
The 74K core permits memory regions to be marked as “uncached accelerated”. This type of region is useful to hard-
ware which is “write only” - perhaps video frame buffers, or some other hardware stream. Sequential word stores in
such regions are gathered into cache-line-sized chunks, before being written with a single burst cycle on the CPU
interface.
Such regions are uncached for read, and partial-word or out-of-sequence writes have “unpredictable” effects - don’t
do them. The burst write is normally performed when software writes to the last location in the memory block or does
an uncached-accelerated write to some other block; but it can also be triggered by a
sync
instruction, a
pref nudge
, a matching load or any exception. If the block is not completely written by the time it’s pushed out, it
will be written using a series of doubleword or smaller write cycles over the 74K core’s 64-bit memory interface.
If you have an L2 cache, regions marked as “uncached accelerated” are L2-uncached.
3.4.4 The cache instruction and software cache management
The 74K core’s caches are not fully “coherent” and require OS intervention at times. The
cache
instruction is the
building block of such OS interventions, and is required for correct handling of DMA data and for cache initializa-
tion. Historically, the
cache
instruction also had a role when writing instructions (unless the programmer takes some
action, those instructions may only be in the D-cache whereas you need them to be fetched through the I-cache when
the time comes). But where possible use
synci
for that purpose, as described in Section 3.4.8 “Cache management
when writing instructions - the “synci” instruction” .
A cache operation instruction is written
cache op,addr
where
addr
is just an address format, written as for a load/
store instruction. Cache operations are privileged and can only run in kernel mode (
synci
works in user mode,
though). Generally we’re not showing you instruction encodings in this book (you have software tools for that stuff)
but in this case it’s probably necessary, so take a look at
Figure 3.1 .
Table 3.3 Cache Code Values
Code Cached? How it Writes Notes
0 cached write-through An unusual choice for a high-speed CPU, probably only for debug
2 uncached
3 cached writeback All normal cacheable areas
7 uncached “Uncached Accel-
erated” Unusual and interesting mode for high-bandwidth write-only hardware; see
Section 3.4.3, "Uncached accelerated writes" . Such writes just bypass the L2
cache, if there is one.
31 26 25 21 20 18 17 16 15 0
cache base op offset
47
register what to do which cache
Figure 3.1 Fields in the encoding of a cache instruction