MIPS MIPS32 74K Series, Programming Manual

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Chapter 3
Programming the MIPS32® 74K™ Core Family, Revision 02.14 29
Memory map, caching, reads, writes and translation
In this chapter:
• Section 3.1, "The memory map" : basic memory map of the system.
• Section 3.3, "Reads, writes and synchronization"
• Section 3.4, "Caches"
• Section 3.6, "Scratchpad memory/SPRAM" : optional on-chip, high-speed memory (particularly useful when
dual-ported to the OCP interface).
• Section 3.8, "The TLB and translation" : how translation is done and supporting CP0 registers.
3.1 The memory map
A 74K core system can be configured with either a TLB (virtual memory translation unit) or a fixed memory map-
ping.
A TLB-equipped sees the memory map described by the [MIPS32] architecture (which will be familiar to anyone
who has used a 32-bit MIPS architecture CPU) and is summarized in Table 3.1 . The TLB gives you access to a full
32-bit physical address on the system interface. More information about the TLB in Section 3.8, "The TLB and
translation" .
Table 3.1 Basic MIPS32® architecture memory map
Segment Virtual range What happens to accesses here?
Name
kuseg
0x0000.0000-0x7FFF.FFFF
The only region accessible to user-privilege programs.
Mapped by TLB entries.
kseg0 0x8000.0000-0x9FFF.FFFF a fixed-mapping window onto physical addresses
0x0000.0000-0x1FFF.FFFF. Almost invariably cache-
able - but in fact other choices are available, and are
selected by
Config[K0] , see Figure 2.1 .
Accessible only to kernel-privilege programs.
kseg1 0xA000.0000-0xBFFF.FFFF a fixed-mapping window onto the same physical
address range 0x0000.0000-0x1FFF.FFFF as “kseg0”
- but accesses here are uncached.
Accessible only to kernel-privilege programs.
kseg2
0xC000.0000-0xDFFF.FFFF
Mapped through TLB, accessible with supervisor or
kernel privilege (hence the alternate name).
sseg
kseg3
0xE000.0000-0xFFFF.FFFF
Mapped through TLB, accessible only with kernel
privileges.