MIPS MIPS32 74K Series, Programming Manual

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3 Programming the MIPS32® 74K™ Core Family, Revision 02.14
Table of Contents
Chapter 1: Introduction ........................................................................................................................ 11
1.1: Chapters of this manual............................................................................................................................. 12
1.2: Conventions............................................................................................................................................... 12
1.3: 74K™ core features................................................................................................................................... 13
1.4: A brief guide to the 74K
™
core implementation ........................................................................................ 14
1.4.1: Notes on pipeline overview diagram (Figure 1.1):............................................................................ 14
1.4.2: Branches and branch delays............................................................................................................ 17
1.4.3: Loads and load-to-use delays .......................................................................................................... 18
1.4.4: Queues, Resource limits and Consequences .................................................................................. 19
Chapter 2: Initialization and identity ................................................................................................... 21
2.1: Probing your CPU - Config CP0 registers ................................................................................................. 21
2.1.1: The Config register........................................................................................................................... 22
2.1.2: The Config1-2 registers.................................................................................................................... 23
2.1.3: The Config3 register......................................................................................................................... 24
2.1.4: The Config6 register......................................................................................................................... 25
2.1.5: CPU-specific configuration — Config7............................................................................................. 26
2.2: PRId register — identifying your CPU type ............................................................................................... 26
Chapter 3: Memory map, caching, reads, writes and translation .................................................... 29
3.1: The memory map ...................................................................................................................................... 29
3.2: Fixed mapping option ................................................................................................................................ 30
3.3: Reads, writes and synchronization............................................................................................................ 30
3.3.1: Read/write ordering and cache/memory data queues in the 74K
™
core ......................................... 30
3.3.2: The “sync” instruction in 74K
™
family cores .................................................................................... 31
3.3.3: Write gathering and “write buffer flushing” in 74K
™
family cores..................................................... 32
3.4: Caches ...................................................................................................................................................... 32
3.4.1: The L2 cache option......................................................................................................................... 32
3.4.2: Cacheability options ......................................................................................................................... 33
3.4.3: Uncached accelerated writes ........................................................................................................... 34
3.4.4: The cache instruction and software cache management................................................................. 34
3.4.5: Cache instructions and CP0 cache tag/data registers ..................................................................... 35
3.4.6: L1 Cache instruction timing.............................................................................................................. 37
3.4.7: L2 cache instruction timing............................................................................................................... 37
3.4.8: Cache management when writing instructions - the “synci” instruction ........................................... 37
3.4.9: Cache aliases................................................................................................................................... 38
3.4.10: Cache locking................................................................................................................................. 39
3.4.11: Cache initialization and tag/data registers ..................................................................................... 39
3.4.12: L23TagLo Regiser.......................................................................................................................... 40
3.4.13: L23DataLo Register ....................................................................................................................... 40
3.4.14: L23DataHi Register........................................................................................................................ 40
3.4.15: TagLo registers in special modes .................................................................................................. 41
3.4.16: Parity error exception handling and the CacheErr register ............................................................ 41
3.4.17: ErrCtl register ................................................................................................................................. 42
3.5: Bus error exception ................................................................................................................................... 43
3.6: Scratchpad memory/SPRAM..................................................................................................................... 44
3.7: Common Device Memory Map .................................................................................................................. 46