MIPS MIPS32 74K Series, Programming Manual

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8.4 Performance counters
Programming the MIPS32® 74K™ Core Family, Revision 02.14 132
19 ALU-pipe bubble issued. The resulting empty pipe-
stage guarantees that some resource will be unused
for a cycle, sometime soon. Used, for example, to
guarantee an opportunity to write
mfc1
data into a
CB.
Reserved
20 Cycles when one instruction is issued. Cycles when two instructions are issued (one ALU,
one AGEN)
21 Out-of-order ALU issue (that is, the instruction
issued is not the oldest in the pool). Out-of-order AGEN issue.
22 Graduated JAR/JALR.HB D-Cache line refill (not LD/ST misses)
23 Cacheable loads. All D-cache accesses (loads, stores, prefetch,
cacheop etc). Will include counts for some instruc-
tions which didn’t graduate.
24 D-Cache writebacks D-Cache misses
25 D-side JTLB accesses D-side JTLB translation fails. Not quite every one
corresponds to an exception: the instruction might be
discarded by someone else’ redirect before it reaches
the exception resolution point.
26 Load/store instruction redirects, which happen when
the load/store follows too closely on a possibly-
matching cacheop. The 74K core’s D-cache has an auxiliary virtual tag,
used to help pick the right line early. When (occa-
sionally) the physical tag check shows some mis-
match, it is treated as a cache miss — in processing
the “miss” we’ll correct the virtual tag for future
accesses. This event counts those bogus “misses.”
27 Reserved
28 L2 cache writebacks L2 cache accesses
29 L2 cache misses L2 cache misses
30 Cycles Fill Store Buffer(FSB) are full and cause a
pipe stall Cycles Fill Store Buffer(FSB) > 1/2 full
31 Cycles Load Data Queue (LDQ) are full and cause a
pipe stall Cycles Load Data Queue(LDQ) > 1/2 full
32 Cycles Writeback Buffer(WBB) are full and cause a
pipe stall Cycles Writeback Buffer(WBB) > 1/2 full
33 Reserved Reserved
34 Reserved Reserved
35 Redirects following optimistic issue of instruction
dependent on load which missed. Counted only when
the dependent instruction graduates Coprocessor load instructions.
36
jr
(not
$31
) instructions graduated.
jr $31
graduated after mispredict.
37 Branch instructions graduated (excluding CP1/CP2
conditional branches). CP1/CP2 conditional branch instructions graduated.
38 Branch-likely instructions graduated Mispredicted branch-likely instructions graduated
Table 8.8 Performance Counter Event Codes in the PerfCtl0-3[Event] field.
Event
No counter0/2 counter1/3