MIPS MIPS32 74K Series, Programming Manual

Page: 80 / 156

6.4 Setting up the FPU and the FPU control registers
Programming the MIPS32® 74K™ Core Family, Revision 02.14 80
Here you get a choice: you can either configure the CPU to depart from IEEE perfection (see the description of the
FCSR[FS,FO,FN]
bits in the notes to Section 6.1, "FPU (co-processor 1) control registers" ), or provide a software
emulator and resign yourself to a small number of “unimplemented” exceptions.
6.4.3 FPU control register maps
There are five FP control registers:
The FP implementation (FIR) register
Figure 6.2 shows the fields in FIR and the read-only values they always have for 74K family FPUs:
Figure 6.2 Fields in the FIR register
The fields have the following meanings:
• FC: “full convert range”: the hardware will complete any conversion operation without running out of bits and
causing an “unimplemented” exception.
• F64/L/W/D/S: this is a 64-bit floating point unit and implements 64-bit integer (“L”), 32-bit integer (“W”), 64-bit
FP double (“D”) and 32-bit FP single (“S”) operations.
• 3D: does not implement the MIPS-3D ASE.
• PS: does not implement the paired-single instructions described in [MIPS64V2]
• Processor ID/Revision: major and minor revisions of the FPU - as is usual with revisions it’s very useful to print
these out from a verbose sign-on message, and rarely a good idea to have software behave differently according
to the values.
Table 6.1 FPU (co-processor 1) control registers
Conventional CP1 ctrl Description
Name reg num
FCSR
31 Extensive control register - the only FPU control register on histori-
cal MIPS CPUs.
Contains all the control bits. But in practice some of them are more
conveniently accessed through
FCCR
,
FEXR
and
FENR
below.
FIR 0 FP implementation register: read-only information about the capa-
bility of this FPU.
FCCR
25 Convenient partial views of FCSR are better structured, and allow
you to update fields without interfering with the operation of inde-
pendent bits.
FCCR
has FP condition codes,
FEXR
contains IEEE exceptional-
condition information (cause and flag bits) you read, and FENR is
IEEE exceptional-condition enables you write.
FEXR
26
FENR
28
31 25 24 23 22 21 20 19 18 17 16 15 8 7 0
0 FC 0 F64 L W 3D PS D S Processor ID Revision
1 1 1 1 0 0 1 1 0x97 whatever