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Memory map, caching, reads, writes and translation

Programming the MIPS32® 74K™ Core Family, Revision 02.14

Of these:

Index

determines which TLB entry is accessed by

tlbwi

. It’s also used for the result of a

tlbp

(the

instruction you use to see whether a particular address would be successfully translated by the CPU).

Index

only

implements enough bits to index the TLB, however big that is; but a

tlbp

which fails to find a match for the speci-

fied virtual address sets bit 31 of

Index

(it’s easy to test for).

Random

is implemented as a full CPU clock-rate downcounter. It won’t decrement below the value of

Wired

(when it

gets there it bounces off and starts again at the highest legal index). In practice, when used inside the TLB refill
exception handler, it delivers a random index into the TLB somewhere between the value of

Wired

and the top.

Wired

can therefore be set to reserve some TLB entries from random replacement - a good place for an OS to keep

translations which must never cause a TLB translation-not-present exception.Previously, a

tlbwr

instruction would

simply write to the TLB entry that the

Random

ture (whose presence is indicated by

Config6

NMRUP

= 1) to put a little more brains behind selecting a TLB entry to be

replaced. A table of the most recently used TLB entries is maintained and the core attempts to avoid selecting one of
those. This avoids replacing often used pages and has been shown to reduce the number of TLB misses in most cases.
Certain workloads, particularly those accessing data sequentially where the working set just exceeds the mappable
capacity of the non-wired TLB entries, may benefit from having a more random replacement where you sometimes
get lucky and find a long unused page not yet replaced. For those applications, this function can be disabled by setting

Config6

NMRUD

= 1, but you are probably better off leaving it alone.

3.8.4 Reading and writing TLB entries - EntryLo0-1, EntryHi and PageMask registers

The TLB is accessed through staging registers which between them represent all the fields in each TLB entry; they’re
called

EntryHi, PageMask

and

EntryLo0-1

. The fields from

EntryHi

and

PageMask

are shown in

Figure 3.12

All these fields act as staging posts for entries being written to or read from the TLB. But some of them are more
magic than that...

EntryHi[VPN2]

: is the page-pair address to be matched by the entry this reads/writes - see above.

However, on a TLB-related exception

VPN2

is automagically set to the virtual address we were trying to translate

when we got the exception. If - as is most often the case - the outcome of the exception handler is to find and install a
translation to that address,

VPN2

(and generally the whole of

EntryHi

) will turn out to already have the right values in

it.

EntryHi[ASID]

: does double-duty. It is used to stage data to and from the TLB, but in normal running software it’s also

the source of the current "ASID" value, used to extend the virtual address to make sure you only get translations for
the current process.

Figure 3.12 Fields in the EntryHi and PageMask registers

29 28

13 12

8 7