MIPS MIPS32 74K Series, Programming Manual

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Floating point unit
79 Programming the MIPS32® 74K™ Core Family, Revision 02.14
as a single operation. There are a rich set of conversion operations. A bewildering variety of compare instructions
record their results in any one of eight condition flags, and there are branch and conditional-move instructions which
test those flags.
You won’t find any higher-level functions: no exponential, log, sine or cosine. This is a RISC instruction set, you’re
expected to get library functions for those things.
6.3 Floating point loads and stores
FP data does not normally pass through the integer registers; the FPU has its own load and store instructions. The
FPU is conceptually a replaceable tenant of coprocessor 1: while arithmetic FP operations get recognizable names
like
add.d
, the load/store instructions will be found under names like
ldc1
in [MIPS64V2] and other formal docu-
mentation. In assembler code, you’ll more often use mnemonics like
l.d
which you’ll find will work just fine.
Because FP-intensive programs are often dealing with one- or two-dimensional arrays of values, the FPU gets special
load/store instructions where the address is formed by adding two registers; they’re called
ldxc1
etc. In assembler
you just use the
l.d
mnemonic with an appropriate address syntax, and all will be well.
6.4 Setting up the FPU and the FPU control registers
There’s a fair amount of state which you set up to change the way the FPU works; this is controlled by fields in the
FPU control registers, described here.
6.4.1 IEEE options
[IEEE754] defines five classes of exceptional result. For each class the programmer can select whether to get an
IEEE-defined “exceptional result” or to be interrupted. Exceptional results are sometimes just normal numbers but
where precision has been lost, but also can be an infinity or NaN (“not-a-number”) value.
Control over the interrupt-or-not options is done through the
FCSR[Enable]
field (or more cleanly through
FENR
,
the same control bits more conveniently presented); see Table 6.1 below.
It’s overwhelmingly popular to keep
FENR
zero and thus never generate an IEEE exception; see Section 6.5, "FPU
pipeline and instruction timing" for why this is a particularly good idea if you want the best performance.
6.4.2 FPU “unimplemented” exceptions (and how to avoid them)
It’s a long-standing feature of the MIPS Architecture that FPU hardware need not support every corner-case of the
IEEE standard. But to ensure proper IEEE compatibility to the software system, an FPU which can’t manage to gen-
erate the correct value in every case must detect a combination of operation and operands it can’t do right. It then
takes an unimplemented exception, which the OS should catch and arrange to software-emulate the offending instruc-
tion.
The 74K core’s FPU will handle everything IEEE can throw at it, except for tiny numbers: it can’t use or produce
non-zero values which are too small for the standard (“normalized”) representation
19
.
19. IEEE754 defines an alternative “denormalized” representation for these numbers.