MIPS MIPS32 74K Series, Programming Manual

Page: 133 / 156

133 Programming the MIPS32® 74K™ Core Family, Revision 02.14
39 Branches graduated Mispredicted branches graduated
40 Integer instructions graduated (includes all no-ops,
even those with side-effects like
ssnop
and
ehb
,
and also includes conditional moves)
FPU instructions graduated (but not counting FPU
load/store)
41 Loads (including FP) graduated Stores graduated (including FP). Of
sc
instructions,
only successful ones are counted.
42
j
/
jal
graduated MIPS16 instructions graduated
43 Co-ops graduated. integer multiply/divides graduated
44 DSP instructions graduated ALU-DSP graduated, result was saturated.
45 DSP branch instructions graduated MDU-DSP graduated, result was saturated
46 Uncached loads graduated. Uncached stores graduated.
47 Reserved Reserved
48 Reserved
49 EJTAG instruction triggers EJTAG data triggers
50 CP1 branches mispredicted. Reserved
51
sc instructions graduated. sc instructions failed.
52
prefetch instructions graduatedat the top of
LSGB.
prefetch instructions which did nothing,
because they hit in the cache.
53 Cycles where no instructions graduated Load misses graduated. Includes Floating Point
Loads.
54 Cycles where one instruction graduated Cycles where two instructions graduated
55 GFifo blocked cycles Floating point stores graduated
56
Number of cycles 0 instructions graduated from the
time a pipekill happened due to mispredict until the
first new instruction graduates. This is an indicator of
the graduation bandwidth loss due to mispredict.
Number of cycles 0 instructions graduated cycles
from the time a pipekill happened due to replay until
the first new instruction graduates. This is an
indicator of the graduation bandwidth loss due to
replay.
57
58 Exceptions taken Replays initiated from graduation
59 Implementation specific CorExtend event. Con-
nected to UDI_perfcnt_event pin of UDI block. Implementation specifc system event. Connect to
SI_PCEvent pin of the core.
60
61 Reserved for CP2 event
62 Implementation-specific event from ISPRAM block.
MIPS standard ISPRAM (see
Section
3.6 “Scratchpad memory/SPRAM” ) does not pro-
vide such an event.
Implementation-specific event from DSPRAM
block. MIPS standard DSPRAM (see
Section
3.6 “Scratchpad memory/SPRAM” ) does not pro-
vide such an event.
63 L2 single-bit errors which were corrected. Reserved
Table 8.8 Performance Counter Event Codes in the PerfCtl0-3[Event] field.
Event
No counter0/2 counter1/3