MIPS MIPS32 74K Series, Programming Manual

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1.4 A brief guide to the 74K
™
core implementation
Programming the MIPS32® 74K™ Core Family, Revision 02.14 14
which allow users to create assembly language mnemonics and C macros for the new instructions. But there’s
very little about the CorExtend ASE in this manual.
1.4 A brief guide to the 74K
™
core implementation
The 74K family is based around a long (14-19 stage) pipeline with dual issue, and executes instructions out-of-order
to maintain progress around short-term dependencies. The longer pipeline allows for a higher frequency than can be
reached by 24K® family cores (in a comparable process), and the more sophisticated instruction scheduling means
that the 74K core also gets more work done per cycle.
Long-pipeline CPUs can trip up on dependencies (they need a result from a previous instruction), on branches (they
don’t know where to fetch the next instructions until the branch instruction is substantially complete), and on loads
(even on cache hits, the data cannot be available for some number of instructions). Earlier MIPS Technologies cores
had no real trouble with dependencies (dependent instructions, in almost all cases, can run in consecutive cycles).
That’s not so in the longer-pipeline 74K core, and its key trick to get around dependencies is out-of-order execution.
But the techniques used to deal with branches and loads still include branch prediction, non-blocking loads and late
writes — all familiar from MIPS Technologies’ 24K and 34K® core families.
Figure 1.1 Overview of The 74K™ Pipeline
1.4.1 Notes on pipeline overview diagram ( Figure 1.1 ):
Although this diagram is considerably simpler (and further abstracted from reality) than those in [SUM] , there is still
a lot to digest. Rectangles and circles with a thick outline are major functional units — the rectangles are the active
I-cache
IFU
IDU
x4
x4
x2
BHT
D-cache
ALU
AGEN GRU
x2
rename
map
loads. stores, etc
out-of-order execution
speculative
fetch
issue
in-order
completion
completion buffers
read data
external
read/write
cache miss data
updates
reg
file
IT ID IS IB DD DR DS DM
AF AM AC AB
EM EA EC ES EB
WB GC
74K pipeline stages
memory pipeline