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Kernel-mode (OS) programming and Release 2 of the MIPS32® Architecture

Programming the MIPS32® 74K™ Core Family, Revision 02.14

If you are remaining with “classic” interrupt mode, it’s still possible to use one shadow set for all exception handlers
- including interrupt handlers - by setting

SRSCtl[ESS]

non-zero.

In “EIC” interrupt mode, this register has no effect and the shadow set number to be used is determined by an input
bus from the interrupt controller.

Software support for shadow registers

Shadow registers work “as if by magic” for short interrupt routines which run entirely in exception mode (that is, with

Status[EXL]

set). The shadow registers are not just efficient because there’s no need to save user registers; the shadow

registers can also be used to hold contextual information for one or more interrupt routines which uses a particular
shadow set. For more ambitious interrupt nesting schemes, software must save and stack copies of

SRSCtl[PSS]

alongside its copies of

EPC

; and it’s entirely up to the software to determine when an interrupt handler can just go

ahead and use a register set, and when it needs to save values on entry and restore them on exit. That’s at least as dif-
ficult as it sounds: shadow sets are probably best used purely for very low-level, high-speed handlers.

5.5 Saving Power

There are basically just a couple of facilities:

In some cores — distinguished by having

Config7[WII]

set to 1 — a

wait

condition will be terminated by an

active interrupt signal, even if that signal is prevented from causing an interrupt by

Status[IE]

being clear. It’s

not immediately obvious why that behavior is useful, but it avoids a tricky race condition for an OS which uses a

wait

instruction in its idle loop. For programming details consult and

Section B.2.1 “The Config7 register”

•

The

Status[RP]

bit: this doesn’t do anything inside the core, but its state is made available at the core interface as

SI_RP

. Logic outside the core is encouraged to use this to control any logic which trades off power for speed -

most often, that will be slowing the master clock input to the CPU.

5.6 The HWREna register - Control user rdhwr access

HWREna

allows the OS to control which (if any) hardware registers are readable in user mode using

rdhwr

The low four bits (3-0) relate to the four registers required by the MIPS32 standard. The two high bits (31-30) are
available for implementation-dependent use.

The whole register is cleared to zero on reset, so that no hardware register is accessible without positive OS clearance.

Figure 5.5 Fields in the HWREna Register

HWREna[Impl]

: Read 0. If there were any implementation-dependent hardware registers, you could control access to

them here. Currently, no 74K family core has any such extra registers.

HWREna[UL]

: Set this bit 1 to permit user programs to obtain the value of the

UserLocal

CP0 register through

rdhwr $29

31 30 29

Impl UL