MIPS MIPS32 74K Series, Programming Manual

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74K™ core features for debug and profiling
111 Programming the MIPS32® 74K™ Core Family, Revision 02.14
DINTsup : whether JTAG-connected probe has a
DINT
signal to interrupt the CPU. Configured by your SoC designer
(who should know) by hard-wiring the core interface signal
EJ_DINTsup
.
The probe can always interrupt the CPU by a JTAG command using the EJTAG_CONTROL[EjtagBrk] , but
DINT
is
much faster, which is useful if you’re cross-triggering one piece of hardware from another. However, it is fed to both
VPEs at once, and it’s unpredictable which of them will take the resulting debug exception (only one can).
ASIDsize : usually
2
(indicating the 8-bit EntryHi[ASID] field size required by the MIPS32 standard), but can be 0 if your
core has been built with the no-TLB option (i.e. a fixed-mapping MMU).
MIPS16 : 1 because the 74K core always supports the MIPS16 instruction set extension.
NoDMA : 1 - MIPS Technologies cores do not provide EJTAG "DMA" (which would allow a probe to directly read and
write anything attached to the 74K core’s OCP interface).
MIPS32/64 : the zero indicates this is a 32-bit CPU.
Type : indicates what type of entity is associated with this TAP and if the TypeInfo field is used.
TypeInfo : identifier information specific to the entity associated with this TAP.
Rocc : "reset occurred" - reads 1 while a reset signal is applied to the CPU - and then the 1 value persists until overwrit-
ten with a zero from the JTAG side. Until the probe reads this as zero most of the other fields are nonsense.
The EJTAG_CONTROL register is shown in Figure 8.7 :
Table 8.3 Fields in the JTAG-accessible EJTAG_CONTROL register
Notes on the fields:
Rocc
: (read/write) is 1 when a CPU reset has occurred since the bit was last cleared. The
Rocc
bit will keep the 1 value
as long as reset is applied. This bit must be cleared by the probe, to acknowledge that the incident was detected. The
EJTAG Control
register is not updated in the Update-DR state unless
Rocc
is 0, or written to 0. This is in order to
ensure proper handling of processor access.
31 30 29 28 24 23 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 0
Rocc Psi Res Res Doze Halt PerRst PRnW PrAcc Res PrRst ProbEn ProbTrap Res EjtagBrk Res DM Res
Figure 8.7 Fields in the JTAG-accessible EJTAG_CONTROL register
31 30 29 28 23 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 0
Rocc Psz 0 Doze Halt PerRst PRnW PrAcc 0 PrRst ProbEn ProbTrap 0 EjtagBrk 0 DM 0