MIPS MIPS32 74K Series, Programming Manual

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5.3 Exception Entry Points
Programming the MIPS32® 74K™ Core Family, Revision 02.14 72
Release 2: relocate all the exception entry points with EBase
The new-with-release 2
EBase
register does two vital jobs: one is to allow software to know which CPU it’s running
on and the other is to relocate the exception entry points. It is primarily supplied for multi-CPU systems (or with a
MIPS MT CPU, for systems using multiple VPEs).
The latter is necessary because CPUs sharing a memory map (as SMP CPUs often do) have their exception entry
points in kseg0. By setting
EBase
differently on each CPU, you can give them distinct exception handlers.
Figure 5.2 Fields in the EBase Register
EBase[VA] : the base address for the exception vectors, adjustable to a resolution of 4Kbytes. See the exception entry
points table for how that moves all the exception entry points. The top two address bits are fixed to “10”, which
means that the base address is constrained to being somewhere in the “unmapped” kseg0/kseg1 memory regions.
By setting EBase on any CPU and/or VPE of a multiprocessor and/or multithreading system to a unique value, that
CPU can have its own unique exception handlers.
Write this field only when Status[BEV] is set, so that any unexpected exception will be handled through the ROM
entry points (otherwise you would be changing the exception address under your own feet, and the results of that are
undefined).
EBase[CPUNum] : On single-threaded CPUs this is just a single "CPU number" field (set by the core interface bus
SI_CPUNum , which the SoC designer will tie to some suitable value).
5.3.1 Summary of exception entry points
The incremental growth of exception entry points has left no one place where all the entry points are summarized; so
here’s
Table 5.1 . But first:
BASE is 0x8000.0000, as it will be where the software, ignoring the EBase register, leaves it at its power-on value —
that’s also compatible with older MIPS CPUs. Otherwise BASE is the 4Kbyte-aligned address found in EBase after
you ignore the low 12 bits...
RBASE is the ROM/reset entry point base, usually
0xBFC0.0000
. However, 74K family cores can be configured to
use a different base address by fixing some input signals to the core. Specifically, if the core is wired with
SI_UseExceptionBase asserted, then RBASE bits 29-12 will be set by the values of the inputs
SI_ExceptionBase[29:12] (the two high bits will be “10” to select the kseg0/kseg1 regions, and the low 12 bits are
always zero). Relocating RBASE is strictly not compliant with the MIPS32 specification and may break all sorts of
useful pieces of software, so it’s not to be done lightly.
DebugVectorAddr is an alternative entry point for debug exceptions. It is specified via a drseg memory mapped register
of the same name and enabled through the Debug Control Register. The probe handler still takes precedence, but this
is higher priority than the regular ROM entry points.
31 30 29 12 11 10 9 0
1 0 VA 0 CPUNum
0