MIPS MIPS32 74K Series, Programming Manual

Page: 73 / 156

Kernel-mode (OS) programming and Release 2 of the MIPS32® Architecture
73 Programming the MIPS32® 74K™ Core Family, Revision 02.14
5.4 Shadow registers
In hardware terms, shadow registers are deceptively simple: just add one or more extra copies of the register file. If
you can automatically change register set on an exception, the exception handler will run with its own context, and
without the overhead of saving and restoring the register values belonging to the interrupted program. On to the
details...
MIPS shadow registers come as one or more extra complete set of 32 general purpose registers. The CPU only
changes register sets on an exception or when returning from an exception with
eret
.
Selecting shadow sets - SRSCtl
The shadow set selectors are in the
SRSCtl
register, shown in Figure 5.3 .
Figure 5.3 Fields in the SRSCtl Register
SRSCtl[HSS]
: the highest-numbered register set available on this CPU (i.e. the number of available register sets minus
one.) If it reads zero, your CPU has just one set of GPR registers and no shadow-set facility.
SRSCtl[EICSS]
: In EIC mode, the external interrupt controller proposes a shadow register set number with each
requested interrupt (nonzero IPL). When the CPU takes an interrupt, the externally-supplied set number determines
the next set and is made visible here in
SRSCtl[EICSS]
until the next interrupt.
The CPU is in EIC mode if
Config3[VEIC]
(indicating the hardware is EIC-compliant), and software has set
Cause[IV]
to enable vectored interrupts. There’s more about EIC mode in Section 5.2.3 “External Interrupt
Controller (EIC) mode” .
Table 5.1 All Exception entry points
Memory region Entry point Exceptions handled here
EJTAG probe-mapped
0xFF20.0200
EJTAG debug, when mapped to “probe” memory.
Alternate Debug Vector DebugVectorAddr EJTAG debug, not probe, relocated, DCR[RDVec] ==1
ROM-only entry points
RBASE+0x0480
EJTAG debug, when using normal ROM memory. DCR[RDVec] ==1
RBASE+0x0000
Post-reset and NMI entry point.
ROM entry points (when
Status[BEV]
==1)
RBASE+0x0200
Simple TLB Refill ( Status[EXL] ==0).
RBASE+0x0300
Cache Error. Note that regardless of any relocation of RBASE (see
above) the cache error entry point is always forced into kseg1.
RBASE+0x0400 Interrupt special (
Cause[IV]
==1).
RBASE+0x0380 All others
“RAM” entry points
( Status[BEV] ==0)
BASE+0x100 Cache error - in RAM. but always through uncached kseg1 window.
BASE+0x000 Simple TLB Refill (
Status[EXL]
==0).
BASE+0x200 Interrupt special (
Cause[IV]
==1).
BASE+0x200+... multiple interrupt entry points - seven more in “VI” mode, 63 in
“EIC” mode; see
Section 5.2, "MIPS32® Architecture Release 2 -
enhanced interrupt system(s)" .
BASE+0x180 All others
31 30 29 26 25 22 21 18 17 16 15 12 11 10 9 6 5 4 3 0
0 HSS 0 EICSS 0 ESS 0 PSS 0 CSS
0 0