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BUS PROTOCOL
4.5.3.
Response Phase Protocol Rules
4.5.3.1.
REQUEST INITIATED TRDY# ASSERTION
A request initiated transaction is a transaction where the request agent has write data to transfer.
The addressed agent asserts TRDY# to indicate its ability to receive data from the request
agent intending to perform a write data operation. Request initiated TRDY# for transaction
“n” is asserted:
•
when the transaction has a write data transfer,
•
a minimum of 3 clocks after ADS# of transaction “n”, and
•
a minimum of 1 clock after RS[2:0]# active assertion for transaction “n-1”. (After the
response for transaction n-1 is driven).
4.5.3.2.
SNOOP INITIATED TRDY# PROTOCOL
The response agent asserts TRDY# to indicate its ability to receive the modified cache line from
a snooping agent. Snoop Initiated TRDY# for transaction “n” is asserted when:
•
the transaction has an implicit writeback data transfer indicated in the Snoop Result Phase.
•
in the case of a request initiated transfer, the request initiated TRDY# was asserted and
then deasserted (TRDY# must be deasserted for at least one clock between the TRDY# for
the write and the TRDY# for the implicit writeback),
•
at least 1 clock has passed after RS[2:0]# active assertion for transaction “n-1” (after the
response for transaction n-1 is driven).
4.5.3.3.
TRDY# DEASSERTION PROTOCOL
The agent asserting TRDY# can deassert it as soon as it can ensure that TRDY# deassertion
meets following conditions.
•
TRDY# may be deasserted when inactive DBSY# and active TRDY# are observed for one
clock.
•
TRDY# can be deasserted within one clock if DBSY# was observed inactive on the clock
TRDY# is asserted and the deassertion is at least three clocks from previous TRDY#
deassertion.
•
TRDY# does not need to be deasserted until the response on RS[2:0]# is asserted.
•
TRDY# for a request initiated transfer must be deasserted to allow the TRDY# for an
implicit writeback.
Summary of Contents for Pentium Pro Family
Page 17: ...1 Component Introduction ...
Page 26: ...2 Pentium Pro Processor Architecture Overview ...
Page 27: ......
Page 36: ...3 Bus Overview ...
Page 62: ...4 Bus Protocol ...
Page 105: ...5 Bus Transactions and Operations ...
Page 126: ...6 Range Registers ...
Page 131: ...7 Cache Protocol ...
Page 135: ...8 Data Integrity ...
Page 148: ...9 Configuration ...
Page 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Page 172: ...11 Electrical Specifications ...
Page 201: ...12 GTL Interface Specification ...
Page 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Page 233: ...14 Thermal Specifications ...
Page 239: ...15 Mechanical Specifications ...
Page 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Page 252: ...16 Tools ...
Page 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Page 264: ...17 OverDrive Processor Socket Specification ...
Page 290: ...A Signals Reference ...
Page 320: ...Index ...
Page 328: ......