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5-14
BUS TRANSACTIONS AND OPERATIONS
an implicit writeback. The response for a transaction that contains an implicit writeback is the
Implicit Writeback response.
5.3.1.1.
MEMORY AGENT RESPONSIBILITIES
On observing HITM# active in the Snoop Phase, the addressed memory agent remains the re-
sponse agent but changes its response to an implicit writeback response.
If the transaction contains a request-initiated data transfer, it remains responsible for TRDY# as-
sertion to indicate that the write data transfer can begin.
Since the transaction contains a snoop-initiated data transfer, (modified line writeback) the
memory agent asserts a snoop initiated TRDY# once it has a free cache line buffer to receive the
modified line writeback (after the TRDY# assertion and deassertion for the request initiated
TRDY# is complete, if there was a request initiated data transfer).
Precisely two clocks from active TRDY# and inactive DBSY#, the Memory Agent drives the im-
plicit writeback response synchronized with the DBSY# assertion from the snooping agent for
the implicit writeback data transfer of the snoop agent.
If the snooped transaction is a write request, the memory agent is responsible for merging the
write data with the writeback cache line. The memory agent then updates main memory with the
latest cache line data. If the snooped transaction writes a full cache line, then there may or may
not be implicit writeback data. If DBSY# is not asserted precisely two clocks from active
TRDY# and inactive DBSY#, then there is no implicit writeback data.
5.3.1.2.
REQUESTING AGENT RESPONSIBILITIES
The requesting agent picks up snoop responsibility for the cache line after observing the trans-
action’s Snoop Phase.
The requesting agent always observes the Response Phase to determine if the snoop-initiated
Data Phase contains additional data beyond what was requested:
•
If the original request is a Part Line Read Transaction, then the requester obtains the
needed data from the first 64-bit critical chunk (as defined by the burst order described in
Chapter 3, Bus Overview).
•
If the original request is a Read Line or Read Invalidate Line Transaction, then the
requester absorbs the entire line.
•
If the original request is an Invalidate Line Transaction and the line is modified in another
cache, then the requester updates its internal cache line with the updated cache line
received in the snoop-initiated Data Phase.
•
If the original Invalidate Line Transaction receives a Deferred Reply, a HITM# in the
Snoop Result Phase indicates data will return, and the requesting agent updates its internal
cache with the data.
Summary of Contents for Pentium Pro Family
Page 17: ...1 Component Introduction ...
Page 26: ...2 Pentium Pro Processor Architecture Overview ...
Page 27: ......
Page 36: ...3 Bus Overview ...
Page 62: ...4 Bus Protocol ...
Page 105: ...5 Bus Transactions and Operations ...
Page 126: ...6 Range Registers ...
Page 131: ...7 Cache Protocol ...
Page 135: ...8 Data Integrity ...
Page 148: ...9 Configuration ...
Page 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Page 172: ...11 Electrical Specifications ...
Page 201: ...12 GTL Interface Specification ...
Page 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Page 233: ...14 Thermal Specifications ...
Page 239: ...15 Mechanical Specifications ...
Page 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Page 252: ...16 Tools ...
Page 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Page 264: ...17 OverDrive Processor Socket Specification ...
Page 290: ...A Signals Reference ...
Page 320: ...Index ...
Page 328: ......